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@ -10,6 +10,7 @@
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#include <asm/arch/omap.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi-mem.h>
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#include <dm.h>
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#include <asm/gpio.h>
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#include <asm/omap_gpio.h>
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@ -40,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define QSPI_INVAL (4 << 16)
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#define QSPI_RD_QUAD (7 << 16)
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/* device control */
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#define QSPI_DD(m, n) (m << (3 + n*8))
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#define QSPI_CKPHA(n) (1 << (2 + n*8))
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#define QSPI_CSPOL(n) (1 << (1 + n*8))
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#define QSPI_CKPOL(n) (1 << (n*8))
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@ -52,22 +52,12 @@ DECLARE_GLOBAL_DATA_PTR;
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#define MM_SWITCH 0x01
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#define MEM_CS(cs) ((cs + 1) << 8)
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#define MEM_CS_UNSELECT 0xfffff8ff
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#define MMAP_START_ADDR_DRA 0x5c000000
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#define MMAP_START_ADDR_AM43x 0x30000000
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#define CORE_CTRL_IO 0x4a002558
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#define QSPI_CMD_READ (0x3 << 0)
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#define QSPI_CMD_READ_DUAL (0x6b << 0)
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#define QSPI_CMD_READ_QUAD (0x6c << 0)
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#define QSPI_CMD_READ_FAST (0x0b << 0)
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#define QSPI_SETUP0_NUM_A_BYTES (0x3 << 8)
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#define QSPI_SETUP0_NUM_D_BYTES_NO_BITS (0x0 << 10)
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#define QSPI_SETUP0_NUM_D_BYTES_8_BITS (0x1 << 10)
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#define QSPI_SETUP0_READ_NORMAL (0x0 << 12)
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#define QSPI_SETUP0_READ_DUAL (0x1 << 12)
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#define QSPI_SETUP0_READ_QUAD (0x3 << 12)
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#define QSPI_CMD_WRITE (0x12 << 16)
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#define QSPI_NUM_DUMMY_BITS (0x0 << 24)
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#define QSPI_SETUP0_ADDR_SHIFT (8)
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#define QSPI_SETUP0_DBITS_SHIFT (10)
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/* ti qspi register set */
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struct ti_qspi_regs {
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@ -98,13 +88,10 @@ struct ti_qspi_regs {
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/* ti qspi priv */
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struct ti_qspi_priv {
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#ifndef CONFIG_DM_SPI
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struct spi_slave slave;
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#else
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void *memory_map;
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size_t mmap_size;
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uint max_hz;
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u32 num_cs;
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#endif
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struct ti_qspi_regs *base;
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void *ctrl_mod_mmap;
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ulong fclk;
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@ -113,8 +100,9 @@ struct ti_qspi_priv {
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u32 dc;
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};
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static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
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static int ti_qspi_set_speed(struct udevice *bus, uint hz)
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{
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struct ti_qspi_priv *priv = dev_get_priv(bus);
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uint clk_div;
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if (!hz)
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@ -133,6 +121,8 @@ static void ti_spi_set_speed(struct ti_qspi_priv *priv, uint hz)
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&priv->base->clk_ctrl);
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/* enable SCLK and program the clk divider */
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writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl);
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return 0;
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}
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static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
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@ -142,38 +132,6 @@ static void ti_qspi_cs_deactivate(struct ti_qspi_priv *priv)
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readl(&priv->base->cmd);
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}
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static int __ti_qspi_set_mode(struct ti_qspi_priv *priv, unsigned int mode)
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{
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priv->dc = 0;
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if (mode & SPI_CPHA)
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priv->dc |= QSPI_CKPHA(0);
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if (mode & SPI_CPOL)
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priv->dc |= QSPI_CKPOL(0);
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if (mode & SPI_CS_HIGH)
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priv->dc |= QSPI_CSPOL(0);
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return 0;
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}
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static int __ti_qspi_claim_bus(struct ti_qspi_priv *priv, int cs)
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{
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writel(priv->dc, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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priv->dc <<= cs * 8;
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writel(priv->dc, &priv->base->dc);
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return 0;
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}
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static void __ti_qspi_release_bus(struct ti_qspi_priv *priv)
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{
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writel(0, &priv->base->dc);
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writel(0, &priv->base->cmd);
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writel(0, &priv->base->data);
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}
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static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
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{
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u32 val;
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@ -186,27 +144,25 @@ static void ti_qspi_ctrl_mode_mmap(void *ctrl_mod_mmap, int cs, bool enable)
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writel(val, ctrl_mod_mmap);
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}
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static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags,
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u32 cs)
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static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
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struct ti_qspi_priv *priv;
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struct udevice *bus;
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uint words = bitlen >> 3; /* fixed 8-bit word length */
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const uchar *txp = dout;
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uchar *rxp = din;
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uint status;
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int timeout;
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unsigned int cs = slave->cs;
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/* Setup mmap flags */
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if (flags & SPI_XFER_MMAP) {
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writel(MM_SWITCH, &priv->base->memswitch);
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, true);
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return 0;
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} else if (flags & SPI_XFER_MMAP_END) {
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writel(~MM_SWITCH, &priv->base->memswitch);
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if (priv->ctrl_mod_mmap)
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ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap, cs, false);
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return 0;
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bus = dev->parent;
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priv = dev_get_priv(bus);
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if (cs > priv->num_cs) {
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debug("invalid qspi chip select\n");
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return -EINVAL;
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}
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if (bitlen == 0)
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@ -294,9 +250,9 @@ static int __ti_qspi_xfer(struct ti_qspi_priv *priv, unsigned int bitlen,
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}
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/* TODO: control from sf layer to here through dm-spi */
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#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
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void spi_flash_copy_mmap(void *data, void *offset, size_t len)
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static void ti_qspi_copy_mmap(void *data, void *offset, size_t len)
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{
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#if defined(CONFIG_TI_EDMA3) && !defined(CONFIG_DMA)
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unsigned int addr = (unsigned int) (data);
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unsigned int edma_slot_num = 1;
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@ -311,187 +267,85 @@ void spi_flash_copy_mmap(void *data, void *offset, size_t len)
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/* disable edma3 clocks */
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disable_edma3_clocks();
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#else
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memcpy_fromio(data, offset, len);
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#endif
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*((unsigned int *)offset) += len;
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}
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#endif
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#ifndef CONFIG_DM_SPI
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static inline struct ti_qspi_priv *to_ti_qspi_priv(struct spi_slave *slave)
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static void ti_qspi_setup_mmap_read(struct ti_qspi_priv *priv, u8 opcode,
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u8 data_nbits, u8 addr_width,
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u8 dummy_bytes)
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{
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return container_of(slave, struct ti_qspi_priv, slave);
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}
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u32 memval = opcode;
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return 1;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* CS handled in xfer */
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return;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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ti_qspi_cs_deactivate(priv);
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}
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void spi_init(void)
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{
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/* nothing to do */
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}
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static void ti_spi_setup_spi_register(struct ti_qspi_priv *priv)
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{
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u32 memval = 0;
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#ifdef CONFIG_QSPI_QUAD_SUPPORT
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struct spi_slave *slave = &priv->slave;
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memval |= (QSPI_CMD_READ_QUAD | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_8_BITS |
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QSPI_SETUP0_READ_QUAD | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS);
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slave->mode |= SPI_RX_QUAD;
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#else
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memval |= QSPI_CMD_READ | QSPI_SETUP0_NUM_A_BYTES |
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QSPI_SETUP0_NUM_D_BYTES_NO_BITS |
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QSPI_SETUP0_READ_NORMAL | QSPI_CMD_WRITE |
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QSPI_NUM_DUMMY_BITS;
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#endif
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writel(memval, &priv->base->setup0);
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct ti_qspi_priv *priv;
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#ifdef CONFIG_AM43XX
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gpio_request(CONFIG_QSPI_SEL_GPIO, "qspi_gpio");
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gpio_direction_output(CONFIG_QSPI_SEL_GPIO, 1);
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#endif
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priv = spi_alloc_slave(struct ti_qspi_priv, bus, cs);
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if (!priv) {
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printf("SPI_error: Fail to allocate ti_qspi_priv\n");
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return NULL;
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}
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priv->base = (struct ti_qspi_regs *)QSPI_BASE;
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priv->mode = mode;
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#if defined(CONFIG_DRA7XX)
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priv->ctrl_mod_mmap = (void *)CORE_CTRL_IO;
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priv->slave.memory_map = (void *)MMAP_START_ADDR_DRA;
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priv->fclk = QSPI_DRA7XX_FCLK;
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#else
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priv->slave.memory_map = (void *)MMAP_START_ADDR_AM43x;
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priv->fclk = QSPI_FCLK;
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#endif
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ti_spi_set_speed(priv, max_hz);
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#ifdef CONFIG_TI_SPI_MMAP
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ti_spi_setup_spi_register(priv);
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#endif
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return &priv->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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free(priv);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
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__ti_qspi_set_mode(priv, priv->mode);
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return __ti_qspi_claim_bus(priv, priv->slave.cs);
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("%s: bus:%i cs:%i\n", __func__, priv->slave.bus, priv->slave.cs);
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__ti_qspi_release_bus(priv);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct ti_qspi_priv *priv = to_ti_qspi_priv(slave);
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debug("spi_xfer: bus:%i cs:%i bitlen:%i flags:%lx\n",
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priv->slave.bus, priv->slave.cs, bitlen, flags);
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return __ti_qspi_xfer(priv, bitlen, dout, din, flags, priv->slave.cs);
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}
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#else /* CONFIG_DM_SPI */
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static void __ti_qspi_setup_memorymap(struct ti_qspi_priv *priv,
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struct spi_slave *slave,
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bool enable)
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{
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u32 memval;
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u32 mode = slave->mode & (SPI_RX_QUAD | SPI_RX_DUAL);
|
|
|
|
|
|
|
|
|
|
if (!enable) {
|
|
|
|
|
writel(0, &priv->base->setup0);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
memval = QSPI_SETUP0_NUM_A_BYTES | QSPI_CMD_WRITE | QSPI_NUM_DUMMY_BITS;
|
|
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
|
case SPI_RX_QUAD:
|
|
|
|
|
memval |= QSPI_CMD_READ_QUAD;
|
|
|
|
|
memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
|
|
|
|
|
switch (data_nbits) {
|
|
|
|
|
case 4:
|
|
|
|
|
memval |= QSPI_SETUP0_READ_QUAD;
|
|
|
|
|
slave->mode |= SPI_RX_QUAD;
|
|
|
|
|
break;
|
|
|
|
|
case SPI_RX_DUAL:
|
|
|
|
|
memval |= QSPI_CMD_READ_DUAL;
|
|
|
|
|
memval |= QSPI_SETUP0_NUM_D_BYTES_8_BITS;
|
|
|
|
|
case 2:
|
|
|
|
|
memval |= QSPI_SETUP0_READ_DUAL;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
memval |= QSPI_CMD_READ;
|
|
|
|
|
memval |= QSPI_SETUP0_NUM_D_BYTES_NO_BITS;
|
|
|
|
|
memval |= QSPI_SETUP0_READ_NORMAL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
memval |= ((addr_width - 1) << QSPI_SETUP0_ADDR_SHIFT |
|
|
|
|
|
dummy_bytes << QSPI_SETUP0_DBITS_SHIFT);
|
|
|
|
|
|
|
|
|
|
writel(memval, &priv->base->setup0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_set_speed(struct udevice *bus, uint max_hz)
|
|
|
|
|
{
|
|
|
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
|
|
|
|
|
|
ti_spi_set_speed(priv, max_hz);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_set_mode(struct udevice *bus, uint mode)
|
|
|
|
|
{
|
|
|
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
|
return __ti_qspi_set_mode(priv, mode);
|
|
|
|
|
|
|
|
|
|
priv->dc = 0;
|
|
|
|
|
if (mode & SPI_CPHA)
|
|
|
|
|
priv->dc |= QSPI_CKPHA(0);
|
|
|
|
|
if (mode & SPI_CPOL)
|
|
|
|
|
priv->dc |= QSPI_CKPOL(0);
|
|
|
|
|
if (mode & SPI_CS_HIGH)
|
|
|
|
|
priv->dc |= QSPI_CSPOL(0);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_exec_mem_op(struct spi_slave *slave,
|
|
|
|
|
const struct spi_mem_op *op)
|
|
|
|
|
{
|
|
|
|
|
struct ti_qspi_priv *priv;
|
|
|
|
|
struct udevice *bus;
|
|
|
|
|
|
|
|
|
|
bus = slave->dev->parent;
|
|
|
|
|
priv = dev_get_priv(bus);
|
|
|
|
|
u32 from = 0;
|
|
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
|
|
/* Only optimize read path. */
|
|
|
|
|
if (!op->data.nbytes || op->data.dir != SPI_MEM_DATA_IN ||
|
|
|
|
|
!op->addr.nbytes || op->addr.nbytes > 4)
|
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
|
|
/* Address exceeds MMIO window size, fall back to regular mode. */
|
|
|
|
|
from = op->addr.val;
|
|
|
|
|
if (from + op->data.nbytes > priv->mmap_size)
|
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
|
|
ti_qspi_setup_mmap_read(priv, op->cmd.opcode, op->data.buswidth,
|
|
|
|
|
op->addr.nbytes, op->dummy.nbytes);
|
|
|
|
|
|
|
|
|
|
ti_qspi_copy_mmap((void *)op->data.buf.in,
|
|
|
|
|
(void *)priv->memory_map + from, op->data.nbytes);
|
|
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_claim_bus(struct udevice *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
|
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
|
|
|
struct ti_qspi_priv *priv;
|
|
|
|
|
struct udevice *bus;
|
|
|
|
|
|
|
|
|
@ -503,42 +357,41 @@ static int ti_qspi_claim_bus(struct udevice *dev)
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
__ti_qspi_setup_memorymap(priv, slave, true);
|
|
|
|
|
writel(MM_SWITCH, &priv->base->memswitch);
|
|
|
|
|
if (priv->ctrl_mod_mmap)
|
|
|
|
|
ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
|
|
|
|
|
slave_plat->cs, true);
|
|
|
|
|
|
|
|
|
|
return __ti_qspi_claim_bus(priv, slave_plat->cs);
|
|
|
|
|
}
|
|
|
|
|
writel(priv->dc, &priv->base->dc);
|
|
|
|
|
writel(0, &priv->base->cmd);
|
|
|
|
|
writel(0, &priv->base->data);
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_release_bus(struct udevice *dev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
|
|
|
struct ti_qspi_priv *priv;
|
|
|
|
|
struct udevice *bus;
|
|
|
|
|
|
|
|
|
|
bus = dev->parent;
|
|
|
|
|
priv = dev_get_priv(bus);
|
|
|
|
|
|
|
|
|
|
__ti_qspi_setup_memorymap(priv, slave, false);
|
|
|
|
|
__ti_qspi_release_bus(priv);
|
|
|
|
|
priv->dc <<= slave_plat->cs * 8;
|
|
|
|
|
writel(priv->dc, &priv->base->dc);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_xfer(struct udevice *dev, unsigned int bitlen,
|
|
|
|
|
const void *dout, void *din, unsigned long flags)
|
|
|
|
|
static int ti_qspi_release_bus(struct udevice *dev)
|
|
|
|
|
{
|
|
|
|
|
struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
|
|
|
|
|
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
|
|
|
|
|
struct ti_qspi_priv *priv;
|
|
|
|
|
struct udevice *bus;
|
|
|
|
|
|
|
|
|
|
bus = dev->parent;
|
|
|
|
|
priv = dev_get_priv(bus);
|
|
|
|
|
|
|
|
|
|
if (slave->cs > priv->num_cs) {
|
|
|
|
|
debug("invalid qspi chip select\n");
|
|
|
|
|
return -EINVAL;
|
|
|
|
|
}
|
|
|
|
|
writel(~MM_SWITCH, &priv->base->memswitch);
|
|
|
|
|
if (priv->ctrl_mod_mmap)
|
|
|
|
|
ti_qspi_ctrl_mode_mmap(priv->ctrl_mod_mmap,
|
|
|
|
|
slave_plat->cs, false);
|
|
|
|
|
|
|
|
|
|
return __ti_qspi_xfer(priv, bitlen, dout, din, flags, slave->cs);
|
|
|
|
|
writel(0, &priv->base->dc);
|
|
|
|
|
writel(0, &priv->base->cmd);
|
|
|
|
|
writel(0, &priv->base->data);
|
|
|
|
|
writel(0, &priv->base->setup0);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_probe(struct udevice *bus)
|
|
|
|
@ -594,12 +447,15 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
|
|
|
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
|
const void *blob = gd->fdt_blob;
|
|
|
|
|
int node = dev_of_offset(bus);
|
|
|
|
|
fdt_addr_t mmap_addr;
|
|
|
|
|
fdt_addr_t mmap_size;
|
|
|
|
|
|
|
|
|
|
priv->ctrl_mod_mmap = map_syscon_chipselects(bus);
|
|
|
|
|
priv->base = map_physmem(devfdt_get_addr(bus),
|
|
|
|
|
sizeof(struct ti_qspi_regs), MAP_NOCACHE);
|
|
|
|
|
priv->memory_map = map_physmem(devfdt_get_addr_index(bus, 1), 0,
|
|
|
|
|
MAP_NOCACHE);
|
|
|
|
|
mmap_addr = devfdt_get_addr_size_index(bus, 1, &mmap_size);
|
|
|
|
|
priv->memory_map = map_physmem(mmap_addr, mmap_size, MAP_NOCACHE);
|
|
|
|
|
priv->mmap_size = mmap_size;
|
|
|
|
|
|
|
|
|
|
priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1);
|
|
|
|
|
if (priv->max_hz < 0) {
|
|
|
|
@ -614,15 +470,9 @@ static int ti_qspi_ofdata_to_platdata(struct udevice *bus)
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int ti_qspi_child_pre_probe(struct udevice *dev)
|
|
|
|
|
{
|
|
|
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
|
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
|
|
|
struct ti_qspi_priv *priv = dev_get_priv(bus);
|
|
|
|
|
|
|
|
|
|
slave->memory_map = priv->memory_map;
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
static const struct spi_controller_mem_ops ti_qspi_mem_ops = {
|
|
|
|
|
.exec_op = ti_qspi_exec_mem_op,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct dm_spi_ops ti_qspi_ops = {
|
|
|
|
|
.claim_bus = ti_qspi_claim_bus,
|
|
|
|
@ -630,6 +480,7 @@ static const struct dm_spi_ops ti_qspi_ops = {
|
|
|
|
|
.xfer = ti_qspi_xfer,
|
|
|
|
|
.set_speed = ti_qspi_set_speed,
|
|
|
|
|
.set_mode = ti_qspi_set_mode,
|
|
|
|
|
.mem_ops = &ti_qspi_mem_ops,
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
static const struct udevice_id ti_qspi_ids[] = {
|
|
|
|
@ -646,6 +497,4 @@ U_BOOT_DRIVER(ti_qspi) = {
|
|
|
|
|
.ofdata_to_platdata = ti_qspi_ofdata_to_platdata,
|
|
|
|
|
.priv_auto_alloc_size = sizeof(struct ti_qspi_priv),
|
|
|
|
|
.probe = ti_qspi_probe,
|
|
|
|
|
.child_pre_probe = ti_qspi_child_pre_probe,
|
|
|
|
|
};
|
|
|
|
|
#endif /* CONFIG_DM_SPI */
|
|
|
|
|