Stop using the findfdt script and switch to setting the fdtfile from
C code.
While at this, replace findfdt in environment with a warning as it is
no longer needed
Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Stop using the findfdt script and switch to setting the fdtfile from
C code.
While at this, replace findfdt in environment with a warning as it is
no longer needed
Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Introduce a common fdt operations library for basic device tree
operations that are common between various boards.
The first library to introduce here is the capability to set up
fdtfile as a standard variable as part of board identification rather
than depend on scripted ifdeffery.
Reviewed-by: Jonathan Humphreys <j-humphreys@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add missing board/ti/common/Kconfig references for the platforms that
missed it. The intent is for the common Kconfig to be usable across TI
reference boards as required.
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
add support for Serial Downloader Boot via UUU as well as flashing emmc
via UUU on USB0 Port of phyBOARD Pollux.
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
With Ethernet DM in place, there is no longer the need for having
the board_phy_config() anymore.
Remove it.
Confirmed that TFTP transfer still works fine without board_phy_config().
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Add new product id 0086 Verdin iMX8M Mini DualLite 2GB IT.
Signed-off-by: Joao Paulo Goncalves <joao.goncalves@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Enrico Leto <enrico.leto@siemens.com> says:
The common folder was initialially created for the common parts of
the products based on draco-am355x board family. We have the
product lines 'pxm2', 'rut' and the base line unfortunately named
'draco'! Adding the new capricorn-imx8 board family, the files
were enhanced without cleanup.
Simplify first EEPROM probe and access that implements both i2c
with & without driver model. Use abstraction functions for this.
Move all am355x specifics to a new file 'board_am335x'.
Clean-up includes, config checks, maintainer.
Adding the capricorn board family some parts diverge from draco family.
The switches used were not pertinent and need to be enhanced for each new
board of the capricorn family. Replace them through the SOC name 'AM33XX'
and 'IMX8'.
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
The common folder was initialially created for the common parts of the
products based on draco-am355x board family. These are the product lines
'pxm2', 'rut' and the base line named 'draco'!
Adding the new capricorn-imx8 board family, common was enhanced without
cleanup.
- rename 'common/board.c' to 'common/board_am335x.c'
- add 'common/board_am335x.h' for export to the product lines
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
NAND was used in the early development phase of etamin. The board runs now
on MMC. This setting is no more used -> remove to simplify the board file.
Further clean-up of etamin should remove all NAND settings. Complete clean-
up of etamin board will take place in a separate patch serie.
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
Since we have boards using the driver model or not for i2c, use abstraction
function to probe the i2c, check the EEPROM and read from EEPROM.
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
Move the I2C and EEPROM address definitions in common board header.
Reviewed-by: Alexander Sverdlin <alexander.sverdlin@siemens.com>
Signed-off-by: Enrico Leto <enrico.leto@siemens.com>
Sonoff iHost is gateway device designed to provide a Smart Home Hub,
it is based on Rockchip RV1126. There is also a version with 2GB RAM
based off the RV1109 dual core SoC however this works with the same
config as the RV1126 for uboot purposes.
Features:
- Rockchip RV1126
- 4GB DDR4
- 8GB eMMC
- microSD slot
- RMII Ethernet PHY
- 1x USB 2.0 Host
- 1x USB 2.0 OTG
- Realtek RTL8723DS WiFi/BT
- EFR32MG21 Silabs Zigbee radio
- Speaker/Microphone
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Configure the pad drive strength register for both PHYs.
The values correspond to what can be found in the Linux DTS
for VisionFive2 v1.3b.
Pad drive strength configuration is required for the phy0 to work correctly
with 100Mbit links.
Signed-off-by: Lukasz Tekieli <tekieli.lukasz@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Add support for Sophgo's Milk-V Duo board, only minimal device tree and
serial console are enabled, and it can boot via vendor first stage
bootloader.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
LEDs and multiple fans can be controlled by SPL. This patch ensures
that all fans have been enabled in the SPL stage. In addition, the
LED's color will be set to yellow.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com>
Co-developed-by: Nylon Chen <nylon.chen@sifive.com>
Signed-off-by: Nylon Chen <nylon.chen@sifive.com>
Co-developed-by: Zong Li <zong.li@sifve.com>
Signed-off-by: Zong Li <zong.li@sifve.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
The difference between the StarFive VisionFive 2 1.2A and 1.3B boards is
handled dynamically by looking at the PCB version in the EEPROM in order
to have a single u-boot version for both versions of the board. While
the "model" property is correctly handled, the "compatible" one is
always the the one of version 1.3b.
This patch add support for dynamically configuring that property.
Fixes: 9b7060bd15 ("riscv: dts: jh7110: Combine the board device tree files of 1.2A and 1.3B")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
In Falcon Boot mode, the fdt blob should be move to the RAM from
kernel BSS section. To avoid being cleared by BSS initialisation.
SPL_PAYLOAD_ARGS_ADDR is the address where SPL copies.
Signed-off-by: Randolph <randolph@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Firmware on RPi5 return error on board revision query
through firmware interface, but on the other hand it fills
"linux,revision" in "system" node, so use it to detect board
revision.
system {
linux,revision = <0xc04170>;
linux,serial = <0x6cf44e80 0x3c533ede>;
};
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Tested-by: Jens Maus <mail@jens-maus.de>
Tested-by: Darko Alavanja <darko.alavanja@konsulko.com>
Signed-off-by: Ivan T. Ivanov <iivanov@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Devarsh Thakkar <devarsht@ti.com> says:
Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.
Also catch the bloblist before starting reservations to avoid the same
problem.
While at it, also fill missing fields in video handoff struct before
passing it to next stage.
This is as per discussions at :
For moving SPL framebuffer reservation at end of RAM:
https://lore.kernel.org/all/CAPnjgZ3xSoe_G3yrqwuAvoiVjUfZ+YQgkOR0ZTVXGT9VK8TwJg@mail.gmail.com/
For filling missing video handoff fields :
https://lore.kernel.org/all/CAPnjgZ1Hs0rNf0JDirp6YPsOQ5=QqQSP9g9qRwLoOASUV8a4cw@mail.gmail.com/
Remove video_setup from evm_init sequence since video memory is getting
called at an earlier place to make sure video memory is reserved at
the end of RAM.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Devarsh Thakkar <devarsht@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add entries for the recently added defconfig files. I had thought I had
committed these updates but lost them before pushing the branch.
Signed-off-by: Tom Rini <trini@konsulko.com>
Drop leading space in front of a comment. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
The header file is not necessary in either of those files,
remove it as common.h is going away.
Include missing asm/arch/rmobile.h in board/renesas/rcar-common/v3-common.c
to prevent build failure of r8a77970_eagle r8a779a0_falcon r8a77980_v3hsk
and r8a77970_v3msk .
Include missing asm/u-boot.h in falcon.c and grpeach.c to fix build failure
due to missing definition of struct bd_info . Include errno.h in grpeach.c
to fix build error due to missing definition of EINVAL.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Paul Barker <paul.barker.ct@bp.renesas.com>
Speed grade T requires the VDD_CORE voltage to be 0.85V if using
the maximum core frequency.
Speed grades G, K, S allow the VDD_CORE voltage to be 0.75V up to the
maximum core frequency but allow to run at 0.85V.
For efficiency in manufacturing and code maintenance we use 0.85V for
the PMIC defaults and device tree settings and dynamically adjust the
voltage in the PMIC and device tree to 0.75V for lower speed SKU to
gain more than 100mW power consumption reduction.
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
EEPROM detection logic in ti_i2c_eeprom_get() involves reading
the total size and the 1-byte size with an offset 1. The commit
9f393a2d7a ("board: ti: common: board_detect: Fix EEPROM read
quirk for 2-byte") that attempts to fix this uses a wrong pointer to
compare.
The value with one offset is read into offset_test, but the pointer
used to match was still ep, resulting in an invalid comparison of the
values. The intent is to identify bad 2-byte addressing eeproms that
get stuck on the successive reads.
Fixes: 9f393a2d7a (board: ti: common: board_detect: Fix EEPROM read quirk for 2-byte)
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Tested-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
The help for CONFIG_MTD explains that it needs to be enabled for various
things like NAND, etc to be available. It however then doesn't enforce
this dependency and so if you have none of these systems present you
still need to disable a number of options. Fix this by making places
that select/imply one type of flash, but did not do the same, also do
this for "MTD". Make boards which hadn't been enabling MTD already but
need it now, do so. In a few places, disable CONFIG_CMD_MTDPARTS as it
wasn't previously enabled but was now being implied.
Signed-off-by: Tom Rini <trini@konsulko.com>
Rather than rely on someone selecting or implying this hidden symbol
that the command requires, select it explicitly.
Signed-off-by: Tom Rini <trini@konsulko.com>
Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.
Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps link.
Additionally add comments documenting each serdes' function of clearfog
gtr, which are shared with clearfog pro.
Signed-off-by: Josua Mayer <josua@solid-run.com>
Clearfog GTR has an assembly option for a SATA connector, CON18.
It shares the serdes with mini-pcie connector CON3.
Add new kconfig option to select betweenata and pci, defaulting to pci
as it was previously configured in board-file.
Clearfog GTR connects eth2 / serdes 1 to a 2.5Gbps capable ethernet
switch port. Linux already configures a fixed-link at speed 2500 from
device-tree.
Upgrade serdes 1 rate to 3.125Gbps to support a 2.5Gbps network link on
Clearfog GTR.
Signed-off-by: Josua Mayer <josua@solid-run.com>
The CONFIG_SPL_BOARD_INIT lets SPL common code call spl_board_init()
during the SPL start up. On this particular system, spl_board_init()
is used to reconfigure GIC clock parent to PLL2 500M, which is the
configuration expected by the Linux kernel. Enable SPL_BOARD_INIT
and fill in the GIC clock configuration code.
Set GIC clock to 500 MHz for OD VDD_SOC. Kernel driver does not
allow to change it. Should set the clock after PMIC setting done.
Default is 400 MHz (system_pll1_800m with div = 2) set by ROM for
ND VDD_SOC.
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Since commit 69b19ca67b ("arm: dts: k3-j721e: Sync with v6.6-rc1"),
the following error message is seen at u-boot
"Sierra init failed:-19"
Probing and initializing the SERDES PHY from
board file is not a clean solution so drop it.
Proper use case should be via PHY_UCLASS APIs.
Signed-off-by: Roger Quadros <rogerq@kernel.org>
STM32MP1:
---------
Set stdio to serial on DH STM32MP15xx DHSOM
Fix reset for usart1 in scmi configuration
STM32MP2:
---------
Add BSEC and OTP support for STM32MP25
Fix CONFIG_STM32MP25X flag usage
-----BEGIN PGP SIGNATURE-----
iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmWqp5scHHBhdHJpY2Uu
Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/ptOaD/0bq6crJ4mND+Ye9zqQ
h4kg/bwPvYQmkYR0OFEmQOSXxuTctlYWvvIdRngSHgGfAEAW6BWt1zvnrKPmzyrI
A4DO4DCTnPkUnFu+yOQ82swsOlQurly+jJy6/bEwwPhHxQFdaVk9epJRsBEFALBE
qU2MCzx0SHZbyPAgCHRly8iXUL413I/YFqi5aMdcUCbFd/K7D7SuH7m35omVdHQx
0ED8wsQOD9dTDvKVQde6wMoo+stB63GjFfM9wZHBKnDsynPk/wyLjozC2JjUB/zS
mAMZXw7OSXpbhmtPdC1hAmAjAQhLI9MF2Tvs5NSDtoLsOBFLsdjGEwfra4/AkyzX
fbOaa+2MP8JlM1vfXxAwhVWhE+hByu9ED5mU7cqICaxXKndu/TUsznXGxNA4+irZ
+ATDhkE8ZAGswJbF80XPJ3+PyxWmy16d3/g0NY4wgHDSP45BCwcStvYhmC2Y2Pdv
O1S4WPzKwgzR7cJ5u6kidHveCc9RVXLhU7nEhjYXZvjBstFDuUhJh/54cDJVcXI5
6Flg1jBh2gdP8p4Odq9CWlJW8TWMEmHn/j7krVApiXtBhhTwaAo+eBSvKk6qpMbs
IgYErA1lIUbkFvDroaptKISavtrRXLvDIG+ladQ6QJ/ki6DYPE2zxsedqd4g2VDh
DZeCtd4nH4/hNFAvdiWxd6woxA==
=BoSU
-----END PGP SIGNATURE-----
Merge tag 'u-boot-stm32-20240119' of https://source.denx.de/u-boot/custodians/u-boot-stm
Add CMDLINE dependecy for CMD_STM32KEY
STM32MP1:
---------
Set stdio to serial on DH STM32MP15xx DHSOM
Fix reset for usart1 in scmi configuration
STM32MP2:
---------
Add BSEC and OTP support for STM32MP25
Fix CONFIG_STM32MP25X flag usage
- A number of OS boot related cleanups, a number of TI platform
fixes/cleanups, SMBIOS fixes, tweak get_maintainers.pl to report me
for more places, fix the "clean the build" pytest and add a bootstage
pytest, fix PKCS11 URI being omitted in some valid cases, make an iommu
problem easier to debug on new platforms, nvme and pci improvements,
refactor image-host code a bit, fix a typo in env setting, add a missing
dependency for CMD_LICENSE, and correct how we call getchar() in some
places.
CONFIG options must not use lower-case letter. Convert this and related
ones to upper case.
Signed-off-by: Simon Glass <sjg@chromium.org
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
CONFIG options must not use lower-case letter. Convert this and related
ones to upper case.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Add the display of the STMicroelectronics board identification saved in OTP
in stm32mp2 checkboard function.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Implement the weak function checkboard to identify the used board with
compatible in device tree for the support of stm32mp2 STMicroelectronics
boards.
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
