Commit graph

13219 commits

Author SHA1 Message Date
Tom Rini
d4c7a9348f Merge branch 'master' of git://git.denx.de/u-boot-net 2018-07-02 16:11:09 -04:00
Rabeeh Khoury
318b5d76b6 net: mvneta: zero Tx descriptors on init
Make the initialization sequence consistent with the Linux kernel
driver.

Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02 14:14:20 -05:00
Rabeeh Khoury
0f8888b763 net: mvneta: dcache flush TX descriptors at init
This fixes sporadic timeout on initial packet Tx (usually ARP), with an
error message like:

  timeout: packet not sent

Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-07-02 14:14:20 -05:00
Michal Simek
d1b226b7d4 net: zynq_gem: Initialize val variable in zynq_gem_miiphy_read()
phyread can timeout and val will contain random value. Initialize it to
zero not to report random value in case of error.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-07-02 14:14:19 -05:00
Tom Rini
6c88079e24 Merge branch 'master' of git://git.denx.de/u-boot-spi 2018-07-02 14:40:03 -04:00
Emmanuel Vadot
425daac481 video: arm: rpi: Add brcm,bcm2708-fb compatible
When using CONFIG_OF_BOARD on rpi to use the dtb provided by the
RaspberryPi Fundation, the compatible string isn't the same, resulting
in not-functional video in u-boot.

Signed-off-by: Oleksandr Tymoshenko <gonzo@FreeBSD.org>
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
2018-07-02 15:23:50 +02:00
Tom Rini
ac378bb05f Merge git://git.denx.de/u-boot-x86 2018-07-01 22:13:34 -04:00
Bin Meng
94e72a6bd9 x86: timer: tsc: Allow specifying clock rate from device tree again
With the introduction of early timer support in the TSC driver,
the capability of getting clock rate from device tree was lost
unfortunately. Now we bring such functionality back, but with a
limitation that when TSC is used as early timer, specifying clock
rate from device tree does not work.

This fixes random boot failures seen on QEMU targets: printing "TSC
frequency is ZERO" and reset forever.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-07-02 09:23:28 +08:00
Jagan Teki
9c22aec410 usb: sunxi: Use proper reg_mask for clock gate, reset
Masking clock gate, reset register bits based on the
probed controller is proper only due to the assumption
that masking should start with 0 even thought the controller
has separate PHY or shared between OTG.

unfortunately these are fixed due to lack of separate
clock, reset drivers.

Say for example EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG)
so we need to start reg_mask 0 - 2.

This patch calculated the mask, based on the register base
so that we can get the proper bits to set with respect to
probed controller.

We even do this masking by using PHY index specifier from dt,
but dev_read_addr_size is failing for 64-bit boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-06-29 10:52:18 +02:00
Zeng Tao
11080bf6c7 usb: ohci: change the NUM_EDs from 8 to 32
For ohci, the maximam supported endpoint number is 32(in and out), and
now we have used (usb_pipeendpoint(pipe) << 1) to index the specified
endpoint descritor, usb_pipeendpoint(pipe) can reach 0xf, so we need
change the NUM_EDs from 8 to 32.

Signed-off-by: Zeng Tao <prime.zeng@hisilicon.com>
2018-06-29 10:52:12 +02:00
Vasily Khoruzhick
ebbc23a049 usb: sunxi: ohci: make ohci_t the first member in private data
ohci-hcd casts priv_data pointer to (ohci_t *), thus it must be
the first member in private data struct.

Fixes 831cc98b1 ("usb: sunxi: Simplify ccm reg base code")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-06-29 10:52:07 +02:00
Marek Vasut
069b746ad9 sf: Enable FSR polling on N25Q256(A)
The N25Q256(A) datasheet clearly states that this device does have
a Flag Status Register and does update FSR PEC bit 7 during Program
and Erase cycles to indicate the cycle is in progress. Enable the
FSR PEC bit polling on this device to prevent data corruption.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Tom Rini <trini@konsulko.com>
2018-06-28 19:58:40 +05:30
Hannes Schmelzer
c0eaffa039 spi: omap3: fix claim/release bus within DM
The claim/release bus function must not reset the whole SPI core because
settings regarding wordlen, clock-frequency and so on made by
set_wordlen, set_mode, set_speed get lost with this action. Resulting in
a non-functional SPI.

Without DM the failure didn't came up since after the spi_reset within
claim bus all the setup (wordlen, mode, ...) was called, in DM they are
called by the spi uclass.

We change now the things as following for having a working SPI instance
in DM:

- move the spi_reset(...) to the probe call in DM for having a known
hardware state after probe. Without DM we don't have a probe call, so we
issue the reset as before during the claim_bus call.

- in release bus we just reset the modulctrl to the reset-value (spi-
slave)

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-28 19:54:10 +05:30
Tom Rini
fb77a9e353 Merge branch 'master' of git://git.denx.de/u-boot-spi 2018-06-28 09:04:41 -04:00
Andrew Thomas
af15946aa0 dwc2 USB controller hangs with lan78xx
This bug is the combination of dwc2 USB controller and lan78xx
USB ethernet controller, which is the combination in use on
the Raspberry Pi Model 3 B+.

When the host attempts to receive a packet, but a packet has not
arrived, the lan78xx controller responds by setting BIR
(Bulk-In Empty Response) to NAK. Unfortunately, this hangs
the USB controller and requires the USB controller to
be reset.

The fix proposed is to have the lan78xx controller respond
by setting BIR to ZLP.

Signed-off-by: Andrew Thomas <andrew.thomas@oracle.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
2018-06-27 22:21:25 -04:00
Tom Rini
de76610545 Merge git://git.denx.de/u-boot-imx 2018-06-27 13:09:55 -04:00
Jörg Krause
4368f85359 mtd: nand: mxs_nand_spl: add mxs_flash_full_ident
For now, the existing SPL MXS NAND driver only supports to identify
ONFi-compliant NAND chips. In order to allow identifying
non-ONFi-compliant chips add `mxs_flash_full_ident()` which uses the
`nand_get_flash_type()` functionality from `nand_base.c` to lookup
for supported NAND chips in the chip ID list.

For compatibility reason the full identification support is only
available if the config option `CONFIG_SPL_NAND_IDENT` is enabled.

The lookup was tested on a custom i.MX6ULL board with a Toshiba
TC58NVG1S3HTAI0 NAND chip.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27 12:20:55 +02:00
Jörg Krause
f3f2af3bdf mtd: nand: mxs_nand_spl: refactor mxs_flash_ident
The existing `mxs_flash_ident()` is limited to identify ONFi compliant
NAND chips only. In order to support non-ONFi NAND chips refactor the
function and rename it to `mxs_flash_onfi_ident()`.

A follow-up patch will add `mxs_flash_full_ident()` which allows to use
the chip ID list to lookup for supported NAND flashs.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27 12:20:55 +02:00
Jörg Krause
15e207faa0 spl, nand: add option CONFIG_SPL_NAND_IDENT to lookup for supported NAND chips
Add the config option `CONFIG_SPL_NAND_IDENT` for using the NAND chip ID list
to identify the NAND flash in SPL.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27 12:20:55 +02:00
Jörg Krause
da37d09682 mtd: nand: export nand_get_flash_type function
`nand_get_flash_type()` allows identification of supported NAND flashs.
The function is useful in SPL (like mxs_nand_spl.c) to lookup for a NAND
flash (which does not support ONFi) instead of using nand_simple.c and
hard-coding all required NAND parameters.

Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks>
2018-06-27 12:20:55 +02:00
Trent Piepho
7da7ff5491 power: pmic: Let PFUZE3000 see all 256 registers
The PFUZE3000 uses registers addresses up to 0xff.

The DM pfuze100 driver supports both pfuze100 and pfuze3000.  Allow it
to use the device type to return the correct number of registers.

Also rename the too generic PMIC_NUM_OF_REGS enumeration value for
pfuze3000 to match the other "PFUZE3000_" prefixed enumerations and the
pfuze100 enumeration value PFUZE100_NUM_OF_REGS.

Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Trent Piepho <tpiepho@impinj.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-27 09:47:46 +02:00
Stefan Agner
627544506f mtd: nand: mxs_nand: add support for specific ECC strength
Add support for specified ECC strength/size using device tree
properties nand-ecc-strength/nand-ecc-step-size.

This aligns behavior with the mainline driver, such that:
- If fsl,use-minimal-ecc is requested it will use data from
  data sheet/ONFI. If this is not available the driver will fail.
- If nand-ecc-strength/nand-ecc-step-size are specified those
  value will be used.
- By default maximum possible ECC strength is used

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
f75e83bfae mtd: nand: mxs_nand: add device tree support
Support driver data from device tree. Also support fsl,use-minimal-ecc
similar to Linux' GPMI NAND driver.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
68748340c8 mtd: nand: mxs_nand: move structs into header file
Move structs into header file so we can use a separate compile
unit for device tree support.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
502bdc6b4f mtd: nand: mxs_nand: add use_minimum_ecc to struct
Add use_minimum_ecc as struct mxs_nand_info field in preparation
for device tree support.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
3b1328a0ad mtd: nand: mxs_nand: separate board/controller init
In preparation for device tree support separate board init
from controller init similar to other raw NAND drivers.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
0d4e9d8be2 mtd: nand: mxs_nand: use more precise function name
This function initializes DMA descriptors so mxs_nand_init_dma is
more precise. It also frees up the rather generic name mxs_nand_init.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
931747e517 mtd: nand: mxs_nand: move register structs to driver data
Move GPMI and BCH register structs to the driver struct mxs_nand_info
in prepartion for device tree support.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
984df7add1 mtd: nand: mxs_nand: add minimal ECC support
Add support for minimum ECC strength supported by the NAND chip.
This aligns with the behavior when using the fsl,use-minimum-ecc
device tree property in Linux.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
5c69dd0730 mtd: nand: mxs_nand: report correct ECC parameters
Report correct ECC parameters back to the stack. Do not report
bytes as we have it not immeaditly available and the Linux version
also does not report it. It seems to have no aversive effect.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
28897e8d21 mtd: nand: mxs_nand: use structure for BCH geometry
Calculate BCH geometry at start and store the information in
a structure. This avoids recalculation on every page access
and allows to calculate ECC relevant information in one place.
This patch does not change ECC layout or driver behavior in
any way.

The patch aligns the driver somewhat with the Linux GPMI NAND
driver which drives the same IP.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
dc0b69fa9f mtd: nand: mxs_nand: allow to enable BBT support
Add config option which allows to enable on flash bad block table
support. This has the same effect as when using the device tree
property "nand-on-flash-bbt" in Linux.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
5346c31e30 mtd: nand: mxs_nand: use self init
Instead of completing initialization via scan_bbt callback use
NAND self init to initialize the GPMI (MXS) NAND controller.

Suggested-by: Scott Wood <oss@buserror.net>
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Stefan Agner
9345943b2b mtd: nand: mxs_nand: introduce SPL specific init
In preparation to convert the driver to use NAND self init
provide a new minimal init for SPL builds. As a side effect
this also reduces size of SPL by about 4KiB.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
2018-06-27 09:07:55 +02:00
Ashish Kumar
51dce7d2bf mtd: spi: Correct parameters for s25fs512s flash
Change sector size to 256KiB in table spi_flash_ids.

Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25 15:50:33 +05:30
Hannes Schmelzer
9cddf70ead spi: omap3: fix set_speed and set_mode dm callbacks
commit 8480792287
("spi: omap3: Skip set_mode, set_speed from claim") did break SPI
support on my AM335x board.

The named commit:

- ignored the responsible arguments (speed, mode)
The set speed/mode function must use the supplied function arguments to
work properly. With this commit we take those arguments and transfer
them to the priv-data.

- used wrong udevice pointer for getting priv data
the udevice-pointer within function argument is already the spi-bus
device, so it is wrong looking here for some parent (ocp-bus in this
case) and getting priv-pointer from there.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25 15:35:15 +05:30
Hannes Schmelzer
b1d2b529b4 spi: omap3: pre-initialize bus-speed with max. slave-speed
Otherwise the frequency is zero and the clock divider cannot be setup by
'omap3_spi_set_speed' function.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25 15:35:01 +05:30
Michael Trimarchi
34ad749141 spi: mxc_spi: Fix chipselect on DM_SPI driver uclass
CS GPIO activation low/high is determinated by the device tree
so we don't need to take in accoung in cs_activate and cs_deactivate

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25 15:23:06 +05:30
Michael Trimarchi
618e8e20c2 spi: mxc: Fix compilation problem of DM_SPI class driver
drivers/spi/mxc_spi.c:507: undefined reference to `dev_get_addr'
linux-ld.bfd: BFD (GNU Binutils) 2.29.1 assertion fail elf32-arm.c:9509

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-25 14:18:41 +05:30
Vipul Kumar
240cd7566e spi: zynq_qspi: Fixed incorrect return value error
This patch replaced "return 0" with "return status" to fix the
incorrect return value error reported by the coverity.

Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
[jagan: rebased on master]
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-06-25 14:13:57 +05:30
Masahiro Yamada
41bacb597e serial: uniphier: set clock rate without clock-frequency property
In Linux, the clock rate of the UART is given by the clock driver.

If you try to follow that in U-Boot, you would end up with adding
more u-boot,dm-pre-reloc properties, and also the clock driver would
be too big for SPL, which is used for UniPhier ARMv7 platform.

The current solution is to add 'clock-frequency' property to the
UART nodes, but it does not exist in the DT files in Linux.  I do
not want to let DT diverge for U-Boot.

Check the SoC compatible and set the clock rate according to it.
This will be helpful to sync DT between Linux and U-Boot.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-23 01:28:15 +09:00
Masahiro Yamada
157736a9ee serial: uniphier: rename struct uniphier_serial_private_data
Just for making it shorter.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-23 01:28:14 +09:00
Masahiro Yamada
25ed0fefa4 reset: uniphier: sync reset data with Linux 4.18-rc1
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-23 01:28:08 +09:00
Tom Rini
dc7df68f21 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-06-21 09:02:35 -04:00
Beniamino Galvani
2e668af553 meson: use the clock driver
Use the clk framework to initialize clocks from drivers that need them
instead of having hardcoded frequencies and initializations from board
code.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-06-19 07:31:47 -04:00
Beniamino Galvani
c0fc1e215c clk: add Amlogic meson clock driver
Introduce a basic clock driver for Amlogic Meson SoCs which supports
enabling/disabling clock gates and getting their frequency.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-06-19 07:31:47 -04:00
Neil Armstrong
0421c9809a adc: meson-saradc: fix regmap_init_mem call
The SARADC driver was merged after the following commit :
commit d35812368a ("regmap: change regmap_init_mem() to take ofnode instead udevice")
Thus breaking build, this patch fixes the regmap_init_mem accordingly.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-06-19 07:31:46 -04:00
Simon Glass
fe996ec066 sandbox: swap_case: Increase number of base address regs
At present the code overruns the bar[] array. Fix this.

At the same time, drop the leading / from the "/spl" path so that we can
run U-Boot SPL with:

   spl/u-boot-spl

rather than requiring:

   /path/to/spl/u-boot-spl

Reported-by: Coverity (CID: 131199)

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-06-19 07:31:44 -04:00
Simon Glass
fb95283931 spi: sandbox: Fix memory leak in sandbox_sf_bind_emul()
Move the strdup() call so that it is only done when we know we will bind
the device.

Reported-by: Coverity (CID: 131216)

Signed-off-by: Simon Glass <sjg@chromium.org>
2018-06-19 07:31:44 -04:00
Marek Vasut
159b329226 net: sh_eth: Support reset GPIO both in mac and phy node
The recent DTs have the PHY reset GPIO in the PHY node rather than
the ethernet MAC node, support extracting the PHY reset GPIO info
from both the PHY node and ethernet MAC node.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Marek Vasut
701db6e9c6 net: ravb: Support reset GPIO both in mac and phy node
The recent DTs have the PHY reset GPIO in the PHY node rather than
the ethernet MAC node, support extracting the PHY reset GPIO info
from both the PHY node and ethernet MAC node.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Marek Vasut
536fb5d47c net: ravb: Filter out supported PHY features
The RAVB only supports 100Full and 1000Full operation, it does not support
10Full or any Half-duplex modes. The PHY could still advertise those features
though, so filter out the PHY features accordingly.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Marek Vasut
c4a8d9ca04 net: ravb: Do not shut down clock in start callback
Do not stop the clock in the start callback in case of failure, keep
them running to also keep the PHY running. The failure could be ie.
PHY failing to negotiate link and if the clock get shut down, another
attempt at bringing the link up would fail. The clock right now are
started in probe function and stopped in remove function, which is
the correct behavior.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
2018-06-19 06:15:55 +02:00
Marek Vasut
5af6541972 pinctrl: renesas: Fix register usage in sh_pfc_{read,write}
The sh_pfc_{read,write}() must operate on the register address directly
rather than on an offset, fix this to prevent illegal access.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-19 06:15:55 +02:00
Adam Ford
b4c3fb087b gpio: omap_gpio: Name GPIO's by bank and index with DM_GPIO
There are multiple GPIO banks with up to 32 pins / bank. When
using 'gpio status -a' to read the pins, this patch displays
both GPIO<bank>_<index> similar to how the device trees
display in addition to displaying  gpio_#

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-06-18 14:43:14 -04:00
Adam Ford
6fef62cc47 block: Add SPL_BLOCK_CACHE and default n
When enabling BLOCK_CACHE on devices with limited RAM during SPL,
some devices may not boot.  This creates an option to enable
block caching in SPL by defaults off.  It is dependent on SPL_BLK

Fixes: 46960ad6d0 ("block: Have BLOCK_CACHE default to y in some cases")

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-06-18 14:43:13 -04:00
Adam Ford
8e51c0f254 dm: gpio: Add DM compatibility to GPIO driver for Davinci
This adds DM_GPIO support for the davinici GPIO driver with
DT support.

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-06-18 14:43:12 -04:00
Tom Rini
378b29cbc6 Merge git://git.denx.de/u-boot-x86 2018-06-18 12:59:46 -04:00
Hannes Schmelzer
8fd05fccc8 drivers/gpio/mxc: fix MXC GPIO name in KConfig
The naming with "UART" is obviously wrong, we fix this here.

Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
2018-06-18 16:50:07 +02:00
Bin Meng
4a08c74697 dm: video: Add an EFI framebuffer driver
This adds a DM video driver for U-Boot as the EFI payload. The driver
makes use of all necessary information from the passed EFI GOP info
to create a linear framebuffer device, as if it were initialized by
U-Boot itself.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2018-06-17 21:16:04 +08:00
Tom Rini
103c45fb0d Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-06-17 09:09:40 -04:00
Tom Rini
a715415bb5 Merge branch 'master' of git://git.denx.de/u-boot-usb 2018-06-16 00:07:37 -04:00
Michal Simek
b729ed0d95 serial: zynq: Make zynq_serial_setbrg static
This function is used only inside this driver that's why should be
static.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
a673025535 serial: zynq: Initialize uart only before relocation
This issue was found when OF_LIVE was enabled that there are scrambled
chars on the console like this:
Chip ID:	zu3eg
Watchdog: Started��j�   sdhci@ff160000: 0, sdhci@ff170000: 1
In:    serial@ff010000

I found a solution for this problem exactly the same as I found later in
serial_msm fixed by:
"serial: serial_msm: initialize uart only before relocation"
(sha1: 7e5ad796bc)

What it is happening is that output TX fifo still contains chars to be
sent and _uart_zynq_serial_init() resets TX fifo even in the middle of
transfer.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
e90d2659e4 serial: zynq: Write chars till output fifo is full
Change logic and put char to fifo till there is a space in output fifo.
Origin logic was that output fifo needs to be empty. It means only one
char was in output queue.
Also remove unused ZYNQ_UART_SR_TXEMPTY macro.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
c9a2c47b91 serial: zynq: Use BIT macros instead of shifts and full hex numbers
Coding style is checking to use BIT macros instead of shifts.
The patch is also fixing the rest of macros which should be BITs instead
of hex numbers.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-15 08:54:05 +02:00
Michal Simek
01fcf01e81 gpio: zynq_gpio: bank description should use unsigned type
Use u32 instead of int for max_bank, bank_min and bank_max. These values
can't be negative that's why no reason to use signed type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:05 +02:00
Michal Simek
b6911780b5 mmc: zynq: Fix tuning_loop_counter type in arasan_sdhci_execute_tuning()
Code around tuning_loop_counter variable expects to go below zero.
That's why this variable can't use unsigned type.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:04 +02:00
Michal Simek
1471fadf69 gpio: zynq: Do not check unsigned type that is >= 0
There is no reason to check that unsigned type that is >= 0.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:54:04 +02:00
Siva Durga Prasad Paladugu
1a7414f626 mmc: sdhci: Fix MMC HS200 tuning command failures
This patch fixes the mmc tuning command failures
when tuning pattern data needs to read back for
comparision against the expected bit pattern.

Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-06-15 08:54:04 +02:00
Michal Simek
56c0e646c4 timer: cadence: Implement timer_get_boot_us
This function is required for adding bootstage support.
Also enable it directly for ZynqMP R5 configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-15 08:06:31 +02:00
Marek Vasut
bf8d2dab38 pinctrl: renesas: Sync Gen3 PFC tables with Linux v4.17
Sync the PFC tables with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 22:35:21 +02:00
Marek Vasut
2e975d8628 pinctrl: renesas: Sync Gen2 PFC tables with Linux v4.17
Sync the PFC tables with Linux v4.17.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00
Marek Vasut
6995fc3aca clk: rmobile: Add R8A77995 RPC clock
Add missing RPC entry into the R8A77995 clock driver tables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00
Marek Vasut
0f4ab201fa clk: rmobile: Add R8A77990 RPC clock
Add missing RPC entry into the R8A77990 clock driver tables.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-14 13:36:33 +02:00
Tom Rini
606fddd76c Merge branch 'master' of git://git.denx.de/u-boot-net 2018-06-14 07:20:41 -04:00
Vasily Khoruzhick
b9f34757db usb: sunxi: access ahb_reset0_cfg in CCM using its offset
struct sunxi_ccm_reg doesn't have ahb_reset0_cfg on sun4i and sun5i,
thus compilation fails with:

drivers/usb/host/ohci-sunxi.c:96:26: error: 'struct sunxi_ccm_reg' has
no member named 'ahb_reset0_cfg'

Access this reg using its offset to fix this issue.

Fixes commit 1ed9c1118 ("usb: sunxi: ehci: get rid of ifdefs")
and commit 56830cee3 ("usb: sunxi: ohci: get rid of ifdefs")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-06-14 12:57:19 +02:00
Michal Simek
5b2c9a6ce3 net: gem: Check return value from memalign/malloc
Functions can return NULL in case of error that's why checking return
value is needed.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:59:04 -05:00
Michal Simek
7674b64d78 net: zynq_gem: Initialize phyreg variable
In case of phyread()/phy_setup_op() timeout code is working with
uninitialized phyreg variable. Initialize this variable to make sure
that code it not working with random value.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:18 -05:00
Michal Simek
b33d4a5fc7 net: zynq_gem: Fix return type for phy...()
wait_for_bit_le32 returns negative value on failure. Fix phy...() to
handle these failures properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Chris Packham
5194ed7edc net: mvgbe: extract common code for SMI wait
Combine repeated code from smi_reg_read/smi_reg_write into a common
function smi_wait_ready.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Quentin Schulz
c61221948c net: designware: set the PS bit when resetting DMA bus in MII configuration
On the SPEAr600 SoC, which has the dwmac1000 variant of the IP block,
the DMA reset never succeeds when a MII PHY is used (no problem with a
GMII PHY). The designware_eth_init() function sets the
DMAMAC_SRST bit in the DMA_BUS_MODE register, and then
polls until this bit clears. When a MII PHY is used, with the current
driver, this bit never clears and the driver therefore doesn't work.

The reason is that the PS bit of the GMAC_CONTROL register should be
correctly configured for the DMA reset to work. When the PS bit is 0,
it tells the MAC we have a GMII PHY, when the PS bit is 1, it tells
the MAC we have a MII PHY.

Doing a DMA reset clears all registers, so the PS bit is cleared as
well. This makes the DMA reset work fine with a GMII PHY. However,
with MII PHY, the PS bit should be set.

We have identified this issue thanks to two SPEAr600 platform:

- One equipped with a GMII PHY, with which the existing driver was
working fine.

- One equipped with a MII PHY, where the current driver fails because
the DMA reset times out.

Note: Taken from https://www.spinics.net/lists/netdev/msg432578.html

Signed-off-by: Quentin Schulz <quentin.schulz@bootlin.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Chris Packham
3cb51dad0d net: phy: mv88e61xx: Force CPU port link up
When connecting to from a CPU direct to a 88e6097 typically RGMII is
used. In order for traffic to actually pass we need to force the link up
so the CPU MAC on the other end will see the link.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Jon Nettleton
199b27bb70 mvebu: neta: align DMA buffers
This makes sure the DMA buffers are properly aligned for the
hardware.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Jon Nettleton <jon@solid-run.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Kunihiko Hayashi
a8927795ef net: add Socionext AVE ethernet driver support
Add driver for Socionext AVE ethernet controller that includes MAC and
MDIO bus supporting RGMII/RMII modes.
The driver behaves the ethernet driver model (DM_ETH) with devicetree.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:17 -05:00
Radu Bulie
98017a1fb5 drivers/net/vsc9953: Initialize action RAM in VCAP complex
VCAP tables must be initialized even if no advanced classification
is used. If no initialization is performed, then ECC error will
be observed by the user when the first packet enters the l2switch.
The error is marked in MPIC_EISR0 -bit 29 which means - Internal RAM
multi-bit ECC error.
This patch fixes the aforementioned ECC error by performing the
initialization of VCAP tables.

Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:16 -05:00
Alex Kiernan
286bea2e85 net: cpsw: ti: Reap completed packets before stopping interface
If you send a final packet just before stopping the interface (e.g. a final
ACK as part of the UDP fastboot protocol), then that packet isn't reliably
delivered onto the wire.

Reap packets prior to stopping the interface to ensure any which are
in-flight make it out. Also remove buffer and len from the call to
cpdma_process() as we weren't using them on their return.

Signed-off-by: Alex Kiernan <alex.kiernan@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:16 -05:00
Vicentiu Galanopulo
552e7c57d0 net/phy/cortina: Add support for CS4223 PHY
Add support for Cortina CS4223 10G PHY
  - As per the CS4223 specs, an EEPROM module is
    connected to the PHY. At startup the PHY reads
    the firmware line and tries to load the firmware
    into the internal memory.
  - This driver reads the EEPROM status
    and checks if firmware has been loaded

Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:15 -05:00
Joe Hershberger
6e35686d89 net: sunxi: Correct MAC address register order
Put the enetaddr data in the same order as it was before the change in
commit ace1520cb5 ("net: sunxi-emac: Write HW address via function")

Reported-by: Udo Maslo <u.maslo@web.de>
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:15 -05:00
Mario Six
5e9d9abe08 tsec: Fix reading phy registers from DT
Bus translations should be applied when reading the address of the sgmii
phy registers from the DT. Use ofnode_get_addr_index instead of the
plain ofnode_read_u32_default to fix this.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
2018-06-13 13:54:15 -05:00
Tom Rini
66398944f5 Merge git://git.denx.de/u-boot-x86 2018-06-13 11:43:59 -04:00
Alexey Brodkin
f8c987f8f1 lib: Add hexdump
Often during debugging session it's very interesting to see
what data we were dealing with. For example what we write or read
to/from memory or peripherals.

This change introduces functions that allow to dump binary
data with one simple function invocation like:
------------------->8----------------
print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len);
------------------->8----------------

which gives us the following:
------------------->8----------------
00000000: f2 b7 c9 88 62 61 75 64 72 61 74 65 3d 31 31 35  ....baudrate=115
00000010: 32 30 30 00 62 6f 6f 74 61 72 67 73 3d 63 6f 6e  200.bootargs=con
00000020: 73 6f 6c 65 3d 74 74 79 53 33 2c 31 31 35 32 30  sole=ttyS3,11520
00000030: 30 6e 38 00 62 6f 6f 74 64 65 6c 61 79 3d 33 00  0n8.bootdelay=3.
00000040: 62 6f 6f 74 66 69 6c 65 3d 75 49 6d 61 67 65 00  bootfile=uImage.
00000050: 66 64 74 63 6f 6e 74 72 6f 6c 61 64 64 72 3d 39  fdtcontroladdr=9
00000060: 66 66 62 31 62 61 30 00 6c 6f 61 64 61 64 64 72  ffb1ba0.loadaddr
00000070: 3d 30 78 38 32 30 30 30 30 30 30 00 73 74 64 65  =0x82000000.stde
00000080: 72 72 3d 73 65 72 69 61 6c 30 40 65 30 30 32 32  rr=serial0@e0022
00000090: 30 30 30 00 73 74 64 69 6e 3d 73 65 72 69 61 6c  000.stdin=serial
000000a0: 30 40 65 30 30 32 32 30 30 30 00 73 74 64 6f 75  0@e0022000.stdou
000000b0: 74 3d 73 65 72 69 61 6c 30 40 65 30 30 32 32 30  t=serial0@e00220
000000c0: 30 30 00 00 00 00 00 00 00 00 00 00 00 00 00 00  00..............
...
------------------->8----------------

Source of hexdump.c was copied from Linux kernel v4.7-rc2.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Anatolij Gustschin <agust@denx.de>
Cc: Mario Six <mario.six@gdsys.cc>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefan Roese <sr@denx.de>
2018-06-13 07:49:12 -04:00
Vasily Khoruzhick
11bb62768d usb: sunxi: sun50i: enable OHCI0 clock when OHCI1 is in use
On A64 OHCI1 clock source is OHCI0 clock, so we need to enable OHCI0
clock when OHCI1 is in use.

Fixes commit dd3228170a ("usb: sunxi: Switch to use generic-phy")

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-06-13 07:33:42 +02:00
Vasily Khoruzhick
56830cee3a usb: sunxi: ohci: get rid of ifdefs
We can use compatibles instead.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-06-13 07:33:42 +02:00
Vasily Khoruzhick
1ed9c11188 usb: sunxi: ehci: get rid of ifdefs
We can use compatibles instead.

Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
2018-06-13 07:33:42 +02:00
Christian Gmeiner
6f95d89c71 dm: pci: Use a 1:1 mapping for bus <-> phy addresses
If U-Boot gets used as coreboot payload all pci resources got
assigned by coreboot. If a dts without any pci ranges gets used
the dm is not able to access pci device memory. To get things
working make use of a 1:1 mapping for bus <-> phy addresses.

This change makes it possible to get the e1000 U-Boot driver
working on a sandybridge device where U-Boot is used as coreboot
payload.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Christian Gmeiner
f2825f6ec0 dm: pci: Make ranges dt property optional
If we use U-Boot as coreboot payload with a generic dts without
any ranges specified we fail in pci pre_probe and our pci bus
is not usable.

So convert decode_regions(..) into a void function and do the simple
error handling there.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed 'u-boot' in the commit message and checkpatch warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Bin Meng
9fddf6c7dd usb: xhci-pci: Fix compiler warning
This fixes the following compiler warning:

  "warning: cast from pointer to integer of different size
  [-Wpointer-to-int-cast]"

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-13 09:50:57 +08:00
Christian Gmeiner
acc2482fd8 x86: tsc: add support for reading CPU freq from cpuid
Starting with cpuid level 0x16 (Skylake-based processors)
it is possible to get CPU base freq via cpuid.

This fixes booting on a skylake based system.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed wrong indention of labels]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2018-06-13 09:50:57 +08:00
Tom Rini
7868909ed5 Merge git://git.denx.de/u-boot-fsl-qoriq 2018-06-12 13:25:24 -04:00
Vinitha V Pillai
2d91b53331 LS1012AFRWY: Add Secure Boot support
Added the following:
1. defconfig for LS1012AFRWY Secure boot
2. PfE Validation support

Signed-off-by: Vinitha V Pillai <vinitha.pillai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-06-11 12:34:45 -07:00
Tom Rini
813d1fb56d Merge branch 'master' of git://git.denx.de/u-boot-ubi 2018-06-08 10:08:20 -04:00
Tom Rini
8da19df5b5 Merge branch 'master' of git://git.denx.de/u-boot-i2c 2018-06-08 10:00:46 -04:00
Ramon Fried
948f32c856 bug.h: introduce WARN_ONCE
Add WARN_ONCE definition to allow single time notification
of warnings to the user.
Taken from Linux kernel (4.17) with slight changes
(Removed __section(.data.once))

Signed-off-by: Ramon Fried <ramon.fried@gmail.com>
[trini: Drop the musb and dwc3 compat versions]
Signed-off-by: Tom Rini <trini@konsulko.com>
2018-06-07 17:08:06 -04:00
Tom Rini
46960ad6d0 block: Have BLOCK_CACHE default to y in some cases
When dealing with filesystems that come from block devices we can get a
noticeable performance gain in some use cases from having the block
cache enabled.  The code paths are valid in other cases when we have BLK
set and may provide wins in raw reads in some use cases, so have this be
default when BLK is enabled.

Signed-off-by: Tom Rini <trini@konsulko.com>
2018-06-07 09:12:26 -04:00
Baruch Siach
173ec35191 i2c: mvtwsi: disable i2c slave on Armada 38x
Equivalent code that disables the hidden i2c0 slave already exists in
the Turris Omnia platform specific code. But this hidden i2c0 slave that
interferes the i2c bus is not board specific. Armada 38x SoCs and at
least some Kirkwood variants are affected as well. Add code to disable
this slave to the i2c bus driver to make it work on all affected
hardware.

Use the bind callback because we want this to always run at boot,
regardless of whether U-Boot uses the i2c bus.

Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
2018-06-07 14:19:55 +02:00
Tom Rini
5b2e9a8cf9 Merge branch 'master' of git://git.denx.de/u-boot-spi 2018-06-06 07:16:43 -04:00
Stefan Roese
78306cba11 mtd: ubi: Add missing newlines in ubi_init()
I just stumbled over some cluttered UBI messages. It seems some newline
chars are missing in the current U-Boot UBI source. Lets fix this
in U-Boot as well (Linux has those fixes already).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Heiko Schocher <hs@denx.de>
2018-06-06 10:25:13 +02:00
Patrice Chotard
6b6255cd8a mach-stm32: Enable SPL_RESET_SUPPORT flag
Since commit 0e373c0ade ("spl: add SPL_RESET_SUPPORT"),
reset is supported in SPL, enable this flag for STM32F SoCs family.

This allows to remove a specific case in RCC mfd driver.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-06-05 20:19:09 -04:00
Chris Packham
d3671dfcdb drivers/rtc: convert mvrtc to DM
Add DM support for the Marvell RTC driver.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-06-05 20:19:09 -04:00
Chris Packham
942bb6e2ad drivers/rtc: prepare mvrtc for DM conversion
Split the rtc_{get,set,reset} functions so that the bodies can be used
in a DM driver.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2018-06-05 20:19:08 -04:00
Carlo Caione
b1f2b72e39 sf: Add support for gd25q32b gigadevice flash
This flash IC is used in some chromebook models
manufactured by Bitland.

Signed-off-by: Carlo Caione <carlo@endlessm.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-04 23:40:04 +05:30
Marek Vasut
8ff4130deb sf: Set current flash bank to 0 in clean_bar()
The clean_bar() function resets the SPI NOR BAR register to 0, but
does not set the flash->curr_bar to 0 , therefore those two can get
out of sync, which could ultimatelly result in corrupted flash content.

The simplest test case is this:

  => mw 0x10000000 0x1234abcd 0x4000
  => sf probe
  => sf erase 0x1000000 0x10000
  => sf write 0x10000000 0x1000000 0x10000

  => sf probe ; sf read 0x12000000 0 0x10000 ; md 0x12000000

That is, erase a sector above the 16 MiB boundary and write it with
random pre-configured data. What will actually happen without this
patch is the sector will be erased, but the data will be written to
BAR 0 offset 0x0 in the flash.

This is because the erase command will call write_bar()+clean_bar(),
which will leave flash->bank_curr = 1 while the hardware BAR registers
will be set to 0 through clean_bar(). The subsequent write will also
trigger write_bar()+clean_bar(), but write_bar checks if the target
bank == flash->bank_curr and if so, does NOT reconfigure the BAR in
the SPI NOR. Since flash->bank_curr is still 1 and out of sync with
the HW, the condition matches, BAR programming is skipped and write
ends up at address 0x0, thus corrupting flash content.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-04 23:31:37 +05:30
Ley Foon Tan
6c353674bd spi: cadence_qspi: Change to use devfdt_get_addr_index()
Change to use devfdt_get_addr_index() function to get fdt address.

Original code has compilation warning below:

drivers/spi/cadence_qspi.c: In function ‘cadence_spi_ofdata_to_platdata’:
drivers/spi/cadence_qspi.c:297:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  plat->regbase = (void *)data[0];
                  ^
drivers/spi/cadence_qspi.c:298:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
  plat->ahbbase = (void *)data[2];
                  ^
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-06-04 23:30:04 +05:30
Tom Rini
809e0e398a Merge branch 'master' of git://git.denx.de/u-boot-sunxi 2018-06-04 08:55:00 -04:00
Emmanuel Vadot
d9b63ea987 video: sunxi: de2: Reserve the fb region in the EFI memory map
If compile with support for the efi loader we need to mark the pages
allocated for the framebuffer as reserved so the kernel won't attempt
to use them for other uses.

Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Alexander Graf <agraf@suse.de>
2018-06-03 15:27:20 +02:00
Tom Rini
040b2583c3 Merge branch 'master' of git://git.denx.de/u-boot-sh 2018-06-02 16:58:27 -04:00
Tom Rini
2a046ff5e9 Merge branch 'master' of git://git.denx.de/u-boot-mips 2018-06-01 16:46:39 -04:00
Tom Rini
582d97b6d3 Xilinx changes for v2018.07 second pull
zynqmp:
 - Show reset reason
 - Remove emulation platform
 - Update pmufw version
 - Simplify mmc bootmode
 - Remove dc2 useless configuration file
 - Cleanup mini config
 - Defconfig syncup
 - zcu100, zcu104 and zcu111 dts fixes
 
 xilinx:
 - Use live-tree functions in some drivers
 - Add support for Avnet Minized and Antminer S9
 
 fpga:
 - Add secure bitstream loading support
 
 mmc:
 - Add hs200 mode support
 
 usb xhci:
 - Header fix
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlsRRy4ACgkQykllyylKDCEovgCdGWsr4XFQfDZxCEMmsg2vyJF2
 0egAnj6Td1k6yTzQPDXwCtExZJfS/vgl
 =QxUz
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2018.07-2' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07 second pull

zynqmp:
- Show reset reason
- Remove emulation platform
- Update pmufw version
- Simplify mmc bootmode
- Remove dc2 useless configuration file
- Cleanup mini config
- Defconfig syncup
- zcu100, zcu104 and zcu111 dts fixes

xilinx:
- Use live-tree functions in some drivers
- Add support for Avnet Minized and Antminer S9

fpga:
- Add secure bitstream loading support

mmc:
- Add hs200 mode support

usb xhci:
- Header fix
2018-06-01 13:50:15 -04:00
Álvaro Fernández Rojas
9ca33ebf1c phy: bcm6318-usbh: convert to use live dt
Also fix bad accents in my name.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
25d8380f22 phy: bcm6368-usbh: convert to use live dt
Also fix bad accents in my name.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
5a1ab87f53 phy: bcm6358-usbh: convert to use live dt
Also fix bad accents in my name.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
50d16bcf33 phy: bcm6348-usbh: convert to use live dt
Also fix bad accents in my name.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
c444afbbef cpu: bmips: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
13a7bfe490 ram: bmips: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
46689a94b2 spi: bcm63xx_hsspi: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
85e1ddbaf0 spi: bcm63xx_spi: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
34c0fc3fab power: domain: bcm6328: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
8994551760 led: bcm6328: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
a15c16f923 led: bcm6358: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
e7e64fa0e6 gpio: bcm6345: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
56d4b706d3 reset: bcm6345: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
2902997b8b clk: bcm6345: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
0f56993788 serial: bcm6345: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
aa8f8250ac watchdog: bcm6345: convert to use live dt
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2018-06-01 15:56:02 +02:00
Álvaro Fernández Rojas
30a90f56c3 dm: core: add functions to get memory-mapped I/O addresses
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2018-06-01 15:56:02 +02:00
Tom Rini
caa2a2e5ab Merge branch 'master' of git://git.denx.de/u-boot-usb 2018-06-01 09:52:15 -04:00
Siva Durga Prasad Paladugu
a18d09ea38 fpga: zynqmp: Add secure bitstream loading for ZynqMP
This patch adds support for loading secure bitstreams on ZynqMP
platforms. The secure bitstream images has to be generated using
Xilinx bootgen tool.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-01 11:37:31 +02:00
Siva Durga Prasad Paladugu
cedd48e2cd cmd: fpga: Add support to load secure bitstreams
This patch adds support to load secure bitstreams(authenticated or
encrypted or both). As of now, this feature is added and tested only
for xilinx bitstreams and the secure bitstream was generated using
xilinx bootgen tool, but the command is defined in more generic way.

Command example to load authenticated and device key
encrypted bitstream is as follows
"fpga loads 0 100000 2000000 0 1"

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-06-01 11:37:31 +02:00
Marek Vasut
34f1dba983 net: ravb: Add R8A77990 E3 compatible
Add new compatible to the Ethernet AVB driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:02 +02:00
Marek Vasut
d629152a9a mmc: renesas-sdhi: Add R8A77990 E3 compatible
Add new compatible to the Uniphier SD driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:02 +02:00
Marek Vasut
60ae40c29e gpio: rmobile: Add R8A77990 E3 compatible
Add new compatible to the GPIO driver for R8A77990 E3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:02 +02:00
Marek Vasut
cb13e46aeb pinctrl: renesas: Initial R8A77990 PFC support
This patch adds initial pinctrl driver to support for the R8A77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:02 +02:00
Takeshi Kihara
634f9f0d30 pinctrl: renesas: Add PORT_GP_11 helper macro
This follows the style of existion PORT_GP_X macros and
will be used by a follow-up patch for the r8a77990 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:01 +02:00
Marek Vasut
0d218efe2b clk: renesas: Add R8A77990 E3 clock tables
Add clock tables for R8A77990 E3 SoC .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:47:01 +02:00
Marek Vasut
716d775286 clk: renesas: Add PE clock handling
The PE clock have two parents, add support for picking the correct
one and deriving the clock from it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Marek Vasut
f0f1de75c9 clk: renesas: Add PLL1 and PLL3 dividers
Add and use the PLL1 and PLL3 dividers.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Marek Vasut
8376e0e6f7 clk: renesas: Pass clock rate around as 64bit number internally
The PLL rate could be in the GHz range, which could overflow a 32bit
data type. Since the hardware is 64bit anyway, pass the clock rates
as 64bit number internally to avoid this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Marek Vasut
15e0918285 clk: renesas: Fix swapped arguments in debug message
The mul and div arguments were reported in reverse order in the debug
message, swap them to fix this.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2018-06-01 09:42:13 +02:00
Siva Durga Prasad Paladugu
843337089e mmc: zynqmp: Add HS200 modes support for ZynqMP
This patch adds HS200 suuport for ZynqMP and enables
the same for ZC1751 DC1 board which has eMMC on it.

Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-05-31 13:50:39 +02:00