Commit graph

654 commits

Author SHA1 Message Date
Simon Glass
13a7db9ab1 x86: Convert arch_fsp_init() to use events
Convert this to use events instead of calling a function directly in the
init sequence.

Rename it to arch_fsp_init_f() to distinguish it from the one that happens
after relocation.

For FSPv2 nothing needs to be done here, so drop the empty function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-31 13:16:54 -04:00
Simon Glass
f72d0d4a2f event: Convert existing spy records to simple
Very few of the existing event-spy records use the arguments they are
passed. Update them to use a simple spy instead, to simplify the code.

Where an adaptor function is currently used, remove it where possible.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-31 13:16:54 -04:00
Tom Rini
7e6e40c572 Prepare v2023.10-rc3
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Merge tag 'v2023.10-rc3' into next

Prepare v2023.10-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>
2023-08-21 17:32:17 -04:00
Heinrich Schuchardt
d768dd8855 common: return type board_get_usable_ram_top
board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2023-08-15 18:21:17 +02:00
Simon Glass
cbb607d2d9 bootstd: Allow display of the x86 setup information
Provide an option to dump this information if available.

Move the funciion prototype to the common x86 header. Allow the command
line to be left out since 'bootflow info' show this itself and it is
not in the correct place in memory until the kernel is actually booted.

Fix a badly aligned heading while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-10 18:34:54 -06:00
Simon Glass
dbfb6c096e x86: i8254: Include required ibmpc.h header
This is needed for this file, so include it here explicitly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
edd53bda53 x86: Drop CFG_SYS_STACK_SIZE
This is only used in one file and the value is the same for both boards
which define it. Use the fixed value of 32KB and drop the CFG. This will
allow removal of the config.h files.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> # Intel Edison
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:12 +08:00
Simon Glass
4099df48a6 x86: Correct copying of BIOS mode information
This is copying beyond the end of the destination buffer. Correct the code
by using the size of the  vesa_mode_info struct. We don't need to copy the
rest of the bytes in the buffer.

This long-standing bug prevents virtio bootdevs working correctly on
qemu-x86 at present.

Fixes: 0ca2426bea ("x86: Add support for running option ROMs natively")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # qemu-x86_64
2023-08-09 23:31:11 +08:00
Simon Glass
ea6eef27ca x86: Run QEMU machine setup in SPL
Call the hardware-init function from QEMU from SPL. This allows the
video BIOS to operate correctly.

Create an x86-wide qemu.h header to avoid having to #ifdef the header
in spl.c

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> # qemu-x86_64
2023-08-09 23:31:11 +08:00
Simon Glass
22080e05fc x86: spl: Drop unwanted debug()
This was left over from some previous debugging. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-09 23:31:11 +08:00
Shiji Yang
ccea96f443 treewide: unify the linker symbol reference format
Now all linker symbols are declared as type char[]. Though we can
reference the address via both the array name 'var' and its address
'&var'. It's better to unify them to avoid confusing developers.
This patch converts all '&var' linker symbol refrences to the most
commonly used format 'var'.

Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2023-08-09 09:21:42 -04:00
Simon Glass
db971a7587 x86: Add a little more info to cbsysinfo
Show the number of records in the table and the total table size in
bytes.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-08-01 10:08:49 +08:00
Bin Meng
3dfa411501 x86: fsp: Use mtrr_set_next_var() for graphics memory
At present this uses mtrr_add_request() & mtrr_commit() combination
to program the MTRR for graphics memory. This usage has two major
issues as below:

- mtrr_commit() will re-initialize all MTRR registers from index 0,
  using the settings previously added by mtrr_add_request() and saved
  in gd->arch.mtrr_req[], which won't cause any issue but is unnecessary
- The way such combination works is based on the assumption that U-Boot
  has full control with MTRR programming (e.g.: U-Boot without any blob
  that does all low-level initialization on its own, or using FSP2 which
  does not touch MTRR), but this is not the case with FSP. FSP programs
  some MTRRs during its execution but U-Boot does not have the settings
  saved in gd->arch.mtrr_req[] and when doing mtrr_commit() it will
  corrupt what was already programmed previously.

Correct this to use mtrr_set_next_var() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-08-01 10:06:46 +08:00
Bin Meng
41fbb34469 x86: Change testing logic of mtrr commit
On Coral U-Boot SPL programs some MTRRs and FSPv2 in U-Boot proper
needs to program MTRRs too. With current testing logic of mtrr
commit in init_cache_f_r(), the mtrr commit is skipped which won't
work as the queued mtrr requests include setup for DRAM regions.

Change the logic to allow such configuration.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Tweak to put back CONFIG_FSP_VERSION2 at top:
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-08-01 10:06:46 +08:00
Simon Glass
dac1fa5c19 x86: Make sure that the LPC is active before SDRAM init
Some boards need to access GPIOs to determine which SDRAM is fitted to the
board, for example chromebook_link. Probe this device (if it exists) to
make sure that this works as expected.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:15 +08:00
Simon Glass
e2e7de8747 x86: Convert some debug statements to use logging
Move from using debug() to log_debug() so that we don't have to use the
__func__ parameter and can access other logging features.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:14 +08:00
Simon Glass
6a32489782 x86: Record the start and end of the tables
The ACPI tables are special in that they are passed to EFI as a separate
piece, independent of other tables.

Also they can be spread over two areas of memory, e.g. with QEMU we end
up with tables kept in high memory as well.

Add new global_data fields to hold this information and update the bdinfo
command to show the table areas.

Move the rom_table_end variable into the loop that uses it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:23:08 +08:00
Simon Glass
8856d613cb x86: Refactor table-writing code a little
The implementation of write_tables() is confusing because it uses the
rom_table_start variable as the address pointer as it progresses.

Rename it to rom_addr to make the code clearer. Move the rom_table_end
variable into the block where it is used.

Also update logging to use the ACPI category, now that it is available.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
e7595aa350 x86: Allow logging to be used in SPL reliably
When global_data is relocated, log_head moves in memory, meaning that
the items in that list point to the wrong place.

Disable logging when making the change, then reenable it afterwards, so
that logging works normally.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
7c10e111c1 x86: Init video in SPL if enabled
When video is required in SPL, set this up ready for use. Ignore any
problems since it may be that video is not actually available and we
still want to continue on to U-Boot proper in that case.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
3525258019 x86: Ensure SPL banner is only shown once
Print the banner in SPL init only if the spl_board_init() function isn't
enabled. The spl_board_init() function is in the same file, but is called
later, by board_init_r().

This avoids printing two banners, which causes tests to fail.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
5345700d2a x86: Allow video-BIOS code to be built for SPL
With qemu-x86_64 we need to run the video BIOS while in 32-bit mode, i.e.
SPL. Add a Kconfig option for this, adjust the Makefile rules and use
CONFIG_IS_ENABLED() where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:12:26 +08:00
Simon Glass
78f24d8f34 x86: Show an error when a BIOS exception occurs
Rather than silently hanging, show an error first. This can happen when
there is something wrong with the video BIOS.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
67884002f4 x86: Correct get_sp() implementation for 64-bit
Use an assembler implementation as is done for i386, so that the results
are equivalent for i386 and x86_64.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
633af11dd6 x86: Show the CPU physical address size with bdinfo
This is useful information so show it with the bdinfo command.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
4fb2536e5b x86: Allow listing MTRRs in SPL
Move MTRR-listing code into a common file so it can be used from SPL.
Update the 'mtrr' command to call it.

Use this in SPL just before adjusting the MTRRs, so we can see the state
set up by the board. Only show it when debug is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 17:08:44 +08:00
Simon Glass
d0dfbf548d x86: zimage: Export the function to obtain the cmdline
Allow reading the command line from a zimage, so that it can be recorded
in the bootflow.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-07-17 13:38:35 +08:00
Simon Glass
c886557c18 x86: Add a function to boot a zimage
Add a direct interface to booting a zimage, so that bootstd can call it
without going through the command-line interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-07-17 13:38:35 +08:00
Simon Glass
50574d42cf spl: Commit MTRRs only in board_init_f_r()
We don't need to commit the SPI-flash MTRR change immediately, since it is
now done in the board_init_f_r(). Also this causes chromebook_link64 to
hang, presumably since we are still running from CAR (Cache-as-RAM) in
SPL. Coral handles this OK, perhaps since it is running from a different
memory area, but it has no effect on Coral anyway.

Drop the extra mtrr_commit() in the SPL implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
80831b2a42 x86: spl: Avoid using init_cache_f_r() from SPL
This function is used by U-Boot proper. It does not set up MTRRs when SPL
is enabled, but we do want this done when it is called from SPL. In fact
it is confusing to use the same function from SPL, since there are quite
a few conditions there.

All init_cache_f_r() really does is commit the MTRRs and set up the cache.
Do this in the SPL's version of this function instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
4e7cbf746f x86: Tidy up address for loading U-Boot from SPL
Use the binman symbols for this, to avoid hard-coding the value. We could
use CONFIG_X86_OFFSET_U_BOOT for the address, but it seems better to
obtain the offset and size through the same mechanism.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
3d0f885a2a x86: spl: Show debugging for BSS
Show the area of memory cleared for BSS, when debugging is enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
392720b429 x86: mrc: Correct SPL debug message
SPL printf() does not normally support %#x so just use %x instead. Hex is
expected in U-Boot anyway.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
b194e432c3 x86: Tidy up availability of string functions
For now, just enable the fast-but-large string functions in 32-boot
U-Boot proper only. Avoid using them in SPL. We cannot use then in 64-bit
builds since we only have 32-bit assembly.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2023-05-11 10:25:29 +08:00
Simon Glass
55171aedda dm: Emit the arch_cpu_init_dm() even only before relocation
The original function was only called once, before relocation. The new
one is called again after relocation. This was not the intent of the
original call. Fix this by renaming and updating the calling logic.

With this, chromebook_link64 makes it through SPL.

Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
2f5210b703 x86: coreboot: Show unimplemented sysinfo tags
Sometimes coreboot adds new tags that U-Boot does not know about. These
are silently ignored, but it is useful to at least know what we are
missing.

Add a way to collect this information. For Brya it shows:

   Unimpl. 38 41 37 34 42 40

These are:

   LB_TAG_PLATFORM_BLOB_VERSION
   LB_TAG_ACPI_CNVS
   LB_TAG_FMAP
   LB_TAG_VBOOT_WORKBUF
   LB_TAG_TYPE_C_INFO
   LB_TAG_BOARD_CONFIG

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
368fd56466 x86: coreboot: Collect the address of the ACPI tables
At present any ACPI tables created by prior-stage firmware are ignored.
It is useful to be able to view these in U-Boot.

Pick this up from the sysinfo tables and display it with the cbsysinfo
command. This allows the 'acpi list' command to work when booting from
coreboot.

Adjust the global_data condition so that acpi_start is available even if
table-generation is disabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2023-05-11 10:25:29 +08:00
Simon Glass
5a2a1d8093 x86: Exit EFI boot services before starting kernel
When running the EFI app, we need to exit boot services before jumping
to Linux.

At some point it may be possible to jump to Linux and pass on the system
table, and:

  * install the device-tree as configuration table
  * use LoadImage() to load the kernel image (e.g. from memory)
  * start the image with StartImage()

This should allow the Linux efistub to be used. For now, this is not
implemented.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25 11:07:22 +01:00
Simon Glass
37c9f9cc86 x86: Support booting a 64-bit kernel from 64-bit U-Boot
Add the missing code to handle this. For a 64-bit kernel the entry
address is 0x200 bytes after the normal entry.

Rename the parameter to boot_linux_kernel() accordingly. Update the
comments to indicate that these are addresses, not pointers.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25 11:07:21 +01:00
Simon Glass
90f2b5abb5 x86: Adjust bootparam.h to be more like linux
This likely came from Linux originally, so update it to match v6.2 more.
This has no functional change.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-25 11:07:21 +01:00
Simon Glass
40b8afe6f6 x86: Add a few more items to bdinfo
Add the timer and vendor/model information.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
644e61448c efi: Support a 64-bit frame buffer address
The current vesa structure only provides a 32-bit value for the frame
buffer. Many modern machines use an address outside the range.

It is still useful to have this common struct, but add a separate
frame-buffer address as well.

Add a comment for vesa_setup_video_priv() while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-03-13 13:53:01 +01:00
Simon Glass
210af54947 Correct SPL uses of LMB
This converts 9 usages of this option to the non-SPL form, since there is
no SPL_LMB defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-10 07:41:39 -05:00
Simon Glass
b8bffe661f Correct SPL uses of BOOTSTAGE_REPORT
This converts 2 usages of this option to the non-SPL form, since there is
no SPL_BOOTSTAGE_REPORT defined in Kconfig

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Simon Glass
ffff21fb27 x86: Correct Chrromebook typo
Fix a typo in a comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
2023-02-09 16:32:25 -05:00
Tom Rini
e8272cbd59 x86: Fix saying arch_cpu_init_dm in debug/docs
The function arch_cpu_init_dm was renamed to fsp_setup_pinctrl in these
cases, so rename debug / docs to match.

Cc: Simon Glass <sjg@chromium.org>
Fixes: 7fe32b3442 ("event: Convert arch_cpu_init_dm() to use events")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2023-01-18 12:46:13 -05:00
Sean Anderson
0db588caf9 x86: fsp: Only compile fsp_save_s3_stack if (SPL_)DM_RTC is enabled
This function calls rtc_write32, which has a different signature
depending on if (SPL_)DM_RTC is enabled or not. This could result in a
mismatch in SPL if DM_RTC was enabled but SPL_DM_RTC, as the non-DM
declaration would still be used in SPL even though the implementation
would be for non-DM_RTC. We are switching to the correct definitions in
the next commit, so this will become a compilation error. Since
fsp_save_s3_stack is not called from SPL, avoid compiling it if
(SPL_)DM_RTC is disabled.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-12-09 14:10:28 -05:00
Tom Rini
65cc0e2a65 global: Move remaining CONFIG_SYS_* to CFG_SYS_*
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do
not easily transition to Kconfig. In many cases they likely should come
from the device tree instead. Move these out of CONFIG namespace and in
to CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-12-05 16:06:08 -05:00
Simon Glass
984639039f Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE
The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE
and this makes it imposible to use CONFIG_VAL().

Rename it to resolve this problem.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-31 11:01:31 -04:00
Michal Suchanek
c726fc01cf dm: treewide: Use uclass_first_device_err when accessing one device
There is a number of users that use uclass_first_device to access the
first and (assumed) only device in uclass.

Some check the return value of uclass_first_device and also that a
device was returned which is exactly what uclass_first_device_err does.

Some are not checking that a device was returned and can potentially
crash if no device exists in the uclass. Finally there is one that
returns NULL on error either way.

Convert all of these to use uclass_first_device_err instead, the return
value will be removed from uclass_first_device in a later patch.

Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-10-17 21:17:12 -06:00