2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2011-07-07 04:29:15 +00:00
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/*
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2012-04-18 19:39:53 +00:00
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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2021-11-09 11:00:38 +00:00
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* Copyright 2020-2021 NXP
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2011-07-07 04:29:15 +00:00
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*/
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/*
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* P2041 RDB board configuration file
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2012-08-14 10:14:51 +00:00
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* Also supports P2040 RDB
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2011-07-07 04:29:15 +00:00
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef CONFIG_RAMBOOT_PBL
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
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#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
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2012-08-09 05:09:59 +00:00
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/* Set 1M boot space */
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
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#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
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2012-08-09 05:09:59 +00:00
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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2011-07-07 04:29:15 +00:00
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/* High Level Configuration Options */
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#ifndef CONFIG_RESET_VECTOR_ADDRESS
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#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
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#endif
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2022-11-16 18:10:29 +00:00
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#define CFG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
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2011-07-07 04:29:15 +00:00
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2011-09-13 09:55:11 +00:00
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#ifndef __ASSEMBLY__
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2020-05-10 17:40:09 +00:00
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#include <linux/stringify.h>
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2011-09-13 09:55:11 +00:00
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#endif
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2011-07-07 04:29:15 +00:00
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_L2CSR0 L2CSR0_L2E
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2011-07-07 04:29:15 +00:00
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2022-11-19 23:45:44 +00:00
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#define CFG_POST CFG_SYS_POST_MEMORY /* test POST memory test */
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2011-07-07 04:29:15 +00:00
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/*
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* Config the L3 Cache as L3 SRAM
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*/
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2022-12-02 21:42:31 +00:00
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#define CFG_SYS_INIT_L3_ADDR CONFIG_TEXT_BASE
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2011-07-07 04:29:15 +00:00
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#ifdef CONFIG_PHYS_64BIT
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2022-12-02 21:42:31 +00:00
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#define CFG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_TEXT_BASE)
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2011-07-07 04:29:15 +00:00
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#else
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_L3_ADDR_PHYS CFG_SYS_INIT_L3_ADDR
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2011-07-07 04:29:15 +00:00
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#endif
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#ifdef CONFIG_PHYS_64BIT
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_DCSRBAR 0xf0000000
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#define CFG_SYS_DCSRBAR_PHYS 0xf00000000ull
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2011-07-07 04:29:15 +00:00
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#endif
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/*
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* DDR Setup
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*/
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_DDR_SDRAM_BASE 0x00000000
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#define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE
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2011-07-07 04:29:15 +00:00
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#define SPD_EEPROM_ADDRESS 0x52
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2022-11-16 18:10:37 +00:00
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#define CFG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
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2011-07-07 04:29:15 +00:00
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/*
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* Local Bus Definitions
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*/
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/* Set the local bus clock 1/8 of platform clock */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_LBC_LCRR LCRR_CLKDIV_8
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2011-07-07 04:29:15 +00:00
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2012-10-26 16:40:15 +00:00
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/*
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* This board doesn't have a promjet connector.
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* However, it uses commone corenet board LAW and TLB.
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* It is necessary to use the same start address with proper offset.
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*/
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FLASH_BASE 0xe0000000
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2011-07-07 04:29:15 +00:00
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#ifdef CONFIG_PHYS_64BIT
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
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2011-07-07 04:29:15 +00:00
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#else
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE
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2011-07-07 04:29:15 +00:00
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#endif
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#define CPLD_BASE 0xffdf0000 /* CPLD registers */
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#ifdef CONFIG_PHYS_64BIT
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#define CPLD_BASE_PHYS 0xfffdf0000ull
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#else
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#define CPLD_BASE_PHYS CPLD_BASE
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#endif
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#define PIXIS_LBMAP_SWITCH 7
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#define PIXIS_LBMAP_MASK 0xf0
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#define PIXIS_LBMAP_SHIFT 4
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#define PIXIS_LBMAP_ALTBANK 0x40
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2012-02-28 23:28:07 +00:00
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/* Nand Flash */
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#ifdef CONFIG_NAND_FSL_ELBC
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_BASE 0xffa00000
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2012-02-28 23:28:07 +00:00
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#ifdef CONFIG_PHYS_64BIT
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_BASE_PHYS 0xfffa00000ull
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2012-02-28 23:28:07 +00:00
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#else
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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2012-02-28 23:28:07 +00:00
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#endif
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_BASE_LIST {CFG_SYS_NAND_BASE}
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2012-02-28 23:28:07 +00:00
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/* NAND flash config */
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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2012-02-28 23:28:07 +00:00
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V) /* valid */
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2022-11-12 22:36:51 +00:00
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#define CFG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
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2012-02-28 23:28:07 +00:00
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| OR_FCM_PGS /* Large Page*/ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR)
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#endif /* CONFIG_NAND_FSL_ELBC */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_FLASH_BANKS_LIST {CFG_SYS_FLASH_BASE_PHYS + 0x8000000}
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2011-07-07 04:29:15 +00:00
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/* define to use L1 as initial stack */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
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2011-07-07 04:29:15 +00:00
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#ifdef CONFIG_PHYS_64BIT
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR
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2011-07-07 04:29:15 +00:00
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/* The assembler doesn't like typecast */
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_RAM_ADDR_PHYS \
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((CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
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CFG_SYS_INIT_RAM_ADDR_PHYS_LOW)
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2011-07-07 04:29:15 +00:00
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#else
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_RAM_ADDR_PHYS CFG_SYS_INIT_RAM_ADDR
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
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#define CFG_SYS_INIT_RAM_ADDR_PHYS_LOW CFG_SYS_INIT_RAM_ADDR_PHYS
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2011-07-07 04:29:15 +00:00
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#endif
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_RAM_SIZE 0x00004000
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2011-07-07 04:29:15 +00:00
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_INIT_SP_OFFSET (CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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2011-07-07 04:29:15 +00:00
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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2022-11-16 18:10:28 +00:00
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#define CFG_SYS_NS16550_CLK (get_bus_freq(0)/2)
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2011-07-07 04:29:15 +00:00
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_BAUDRATE_TABLE \
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2011-07-07 04:29:15 +00:00
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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2022-11-16 18:10:41 +00:00
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#define CFG_SYS_NS16550_COM1 (CFG_SYS_CCSRBAR+0x11C500)
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#define CFG_SYS_NS16550_COM2 (CFG_SYS_CCSRBAR+0x11C600)
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#define CFG_SYS_NS16550_COM3 (CFG_SYS_CCSRBAR+0x11D500)
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#define CFG_SYS_NS16550_COM4 (CFG_SYS_CCSRBAR+0x11D600)
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2011-07-07 04:29:15 +00:00
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/* I2C */
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2020-05-01 12:04:05 +00:00
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2011-07-07 04:29:15 +00:00
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/*
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* RapidIO
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*/
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
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2011-07-07 04:29:15 +00:00
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#ifdef CONFIG_PHYS_64BIT
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
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2011-07-07 04:29:15 +00:00
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#else
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000
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2011-07-07 04:29:15 +00:00
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#endif
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
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2011-07-07 04:29:15 +00:00
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
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2011-07-07 04:29:15 +00:00
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#ifdef CONFIG_PHYS_64BIT
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
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2011-07-07 04:29:15 +00:00
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#else
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000
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2011-07-07 04:29:15 +00:00
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#endif
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2022-11-16 18:10:40 +00:00
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#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
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2011-07-07 04:29:15 +00:00
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2012-08-09 05:09:59 +00:00
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/*
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* for slave u-boot IMAGE instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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2022-11-16 18:10:40 +00:00
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#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
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#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
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#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
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#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
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2012-08-09 05:09:59 +00:00
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/*
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* for slave UCODE and ENV instored in master memory space,
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* PHYS must be aligned based on the SIZE
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*/
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2022-11-16 18:10:40 +00:00
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#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
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#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
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#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
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2012-08-09 05:09:59 +00:00
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/* slave core release by master*/
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2022-11-16 18:10:40 +00:00
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#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
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#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
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2012-08-09 05:09:59 +00:00
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/*
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powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
|
|
|
* SRIO_PCIE_BOOT - SLAVE
|
2012-08-09 05:09:59 +00:00
|
|
|
*/
|
powerpc/corenet_ds: Slave module for boot from PCIE
When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.
Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.
NOTE: Because the slave can not erase, write master's NOR flash by
PCIE interface, so it can not modify the ENV parameters stored
in master's NOR flash using "saveenv" or other commands.
environment and requirement:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image is in master NOR flash.
3. Put the slave's ucode and ENV into it's own memory space.
4. Normally boot from local NOR flash.
5. Configure PCIE system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to one PCIE interface by RCW.
3. RCW should configure the SerDes, PCIE interfaces correctly.
4. Must set all the cores in holdoff by RCW.
5. Must be powered on before master's boot.
For the slave module, need to finish these processes:
1. Set the boot location to one PCIE interface by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID of one PCIE for the boot.
4. Set a specific TLB entry in order to fetch ucode and ENV from
master.
5. Set a LAW entry with the TargetID one of the PCIE ports for
ucode and ENV.
6. Slave's u-boot image should be generated specifically by
make xxxx_SRIO_PCIE_BOOT_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
1. Updated the README.srio-boot-corenet to add descriptions about
boot from PCIE, and change the name to
README.srio-pcie-boot-corenet.
2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
"xxxx_SRIO_PCIE_BOOT", and the image builded with
"xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
from PCIE.
3. Updated other macros and documents if needed to add information
about boot from PCIE.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2012-08-09 05:10:03 +00:00
|
|
|
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
|
2022-11-16 18:10:40 +00:00
|
|
|
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
|
|
|
|
|
#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
|
|
|
|
|
(0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
|
2012-08-09 05:09:59 +00:00
|
|
|
#endif
|
|
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
/*
|
|
|
|
|
* eSPI - Enhanced SPI
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* General PCI
|
|
|
|
|
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
2022-11-16 18:10:33 +00:00
|
|
|
#define CFG_SYS_PCIE1_MEM_VIRT 0x80000000
|
|
|
|
|
#define CFG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
|
|
|
|
#define CFG_SYS_PCIE1_IO_VIRT 0xf8000000
|
|
|
|
|
#define CFG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
2022-11-16 18:10:33 +00:00
|
|
|
#define CFG_SYS_PCIE2_MEM_VIRT 0xa0000000
|
|
|
|
|
#define CFG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
|
|
|
|
|
#define CFG_SYS_PCIE2_IO_VIRT 0xf8010000
|
|
|
|
|
#define CFG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
2022-11-16 18:10:33 +00:00
|
|
|
#define CFG_SYS_PCIE3_MEM_VIRT 0xc0000000
|
|
|
|
|
#define CFG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
/* Qman/Bman */
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_BMAN_NUM_PORTALS 10
|
|
|
|
|
#define CFG_SYS_BMAN_MEM_BASE 0xf4000000
|
2011-07-07 04:29:15 +00:00
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
2011-07-07 04:29:15 +00:00
|
|
|
#else
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_BMAN_MEM_PHYS CFG_SYS_BMAN_MEM_BASE
|
2011-07-07 04:29:15 +00:00
|
|
|
#endif
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_BMAN_MEM_SIZE 0x00200000
|
|
|
|
|
#define CFG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
|
|
|
|
#define CFG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
|
|
|
|
#define CFG_SYS_BMAN_CENA_BASE CFG_SYS_BMAN_MEM_BASE
|
|
|
|
|
#define CFG_SYS_BMAN_CENA_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CFG_SYS_BMAN_CINH_BASE (CFG_SYS_BMAN_MEM_BASE + \
|
|
|
|
|
CFG_SYS_BMAN_CENA_SIZE)
|
|
|
|
|
#define CFG_SYS_BMAN_CINH_SIZE (CFG_SYS_BMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CFG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
|
|
|
|
#define CFG_SYS_QMAN_NUM_PORTALS 10
|
|
|
|
|
#define CFG_SYS_QMAN_MEM_BASE 0xf4200000
|
2011-07-07 04:29:15 +00:00
|
|
|
#ifdef CONFIG_PHYS_64BIT
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_QMAN_MEM_PHYS 0xff4200000ull
|
2011-07-07 04:29:15 +00:00
|
|
|
#else
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_QMAN_MEM_PHYS CFG_SYS_QMAN_MEM_BASE
|
2011-07-07 04:29:15 +00:00
|
|
|
#endif
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_QMAN_MEM_SIZE 0x00200000
|
|
|
|
|
#define CFG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
|
|
|
|
#define CFG_SYS_QMAN_CENA_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CFG_SYS_QMAN_CINH_BASE (CFG_SYS_QMAN_MEM_BASE + \
|
|
|
|
|
CFG_SYS_QMAN_CENA_SIZE)
|
|
|
|
|
#define CFG_SYS_QMAN_CINH_SIZE (CFG_SYS_QMAN_MEM_SIZE >> 1)
|
|
|
|
|
#define CFG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_FMAN_ENET
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
|
|
|
|
|
#define CFG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
|
|
|
|
|
#define CFG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
|
|
|
|
|
#define CFG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
|
|
|
|
|
#define CFG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
|
2011-07-07 04:29:15 +00:00
|
|
|
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
|
|
|
|
|
#define CFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
|
|
|
|
|
#define CFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
|
|
|
|
|
#define CFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
|
2011-07-07 04:29:15 +00:00
|
|
|
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_FM1_10GEC1_PHY_ADDR 0
|
2011-07-19 08:20:13 +00:00
|
|
|
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_TBIPA_VALUE 8
|
2011-07-07 04:29:15 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_MMC
|
2022-10-29 00:27:13 +00:00
|
|
|
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
|
2011-07-07 04:29:15 +00:00
|
|
|
#endif
|
2014-10-15 06:05:31 +00:00
|
|
|
|
2011-07-07 04:29:15 +00:00
|
|
|
/*
|
|
|
|
|
* Miscellaneous configurable options
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* For booting Linux, the board info and command line data
|
|
|
|
|
* have to be in the first 64 MB of memory, since this is
|
|
|
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
|
|
|
*/
|
2022-11-16 18:10:41 +00:00
|
|
|
#define CFG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Environment Configuration
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define __USB_PHY_TYPE utmi
|
|
|
|
|
|
2022-12-04 15:03:50 +00:00
|
|
|
#define CFG_EXTRA_ENV_SETTINGS \
|
2011-07-07 04:29:15 +00:00
|
|
|
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
|
|
|
|
|
"bank_intlv=cs0_cs1\0" \
|
|
|
|
|
"netdev=eth0\0" \
|
2022-12-02 21:42:27 +00:00
|
|
|
"uboot=" CONFIG_UBOOTPATH "\0" \
|
2022-10-21 00:22:39 +00:00
|
|
|
"ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \
|
2011-07-07 04:29:15 +00:00
|
|
|
"tftpflash=tftpboot $loadaddr $uboot && " \
|
|
|
|
|
"protect off $ubootaddr +$filesize && " \
|
|
|
|
|
"erase $ubootaddr +$filesize && " \
|
|
|
|
|
"cp.b $loadaddr $ubootaddr $filesize && " \
|
|
|
|
|
"protect on $ubootaddr +$filesize && " \
|
|
|
|
|
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
|
|
|
|
"consoledev=ttyS0\0" \
|
2012-09-23 15:41:24 +00:00
|
|
|
"usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
|
2011-07-07 04:29:15 +00:00
|
|
|
"usb_dr_mode=host\0" \
|
|
|
|
|
"ramdiskaddr=2000000\0" \
|
|
|
|
|
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
|
2016-07-19 22:52:06 +00:00
|
|
|
"fdtaddr=1e00000\0" \
|
2011-07-07 04:29:15 +00:00
|
|
|
"fdtfile=p2041rdb/p2041rdb.dtb\0" \
|
2014-05-15 00:33:45 +00:00
|
|
|
"bdev=sda3\0"
|
2011-07-07 04:29:15 +00:00
|
|
|
|
|
|
|
|
#include <asm/fsl_secure_boot.h>
|
|
|
|
|
|
|
|
|
|
#endif /* __CONFIG_H */
|
