Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2025-02-17 22:49:02 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/configs/phycore-imx8mm_defconfig

131 lines
3.3 KiB
Text
Raw Normal View History

board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
Rename CONFIG_SYS_TEXT_BASE to CONFIG_TEXT_BASE The current name is inconsistent with SPL which uses CONFIG_SPL_TEXT_BASE and this makes it imposible to use CONFIG_VAL(). Rename it to resolve this problem. Signed-off-by: Simon Glass <sjg@chromium.org>
2022-10-20 18:22:39 -06:00
CONFIG_TEXT_BASE=0x40200000
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-01 12:19:22 +00:00
CONFIG_SYS_MALLOC_LEN=0x2000000
Rename GPIO_SUPPORT to GPIO Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-10 21:14:30 -06:00
CONFIG_SPL_GPIO=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-01 11:50:26 -04:00
CONFIG_SF_DEFAULT_SPEED=80000000
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x3C0000
CONFIG_DM_GPIO=y
arm: dts: imx8mm-phyboard-polis-rdk: Sync dts files with kernel Sync the devicetree files used in the kernel for the imx8mm-phyboard-polis with the corresponding devicetree files in U-Boot. Replaced phycore-imx8mm.dts with kernel dts imx8mm-phyboard-polis-rdk.dts Synced with kernel 6.5.0-rc1 commit e752a4f9589c (arm64: dts: freescale: imx8mm-phyboard: Add I2C4 pinmuxing) Signed-off-by: Cem Tenruh <c.tenruh@phytec.de>
2023-07-14 10:23:26 +02:00
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-phyboard-polis-rdk"
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_PHYCORE_IMX8MM=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-05-29 10:43:26 -04:00
CONFIG_SYS_MONITOR_LEN=524288
mmc: Rename MMC_SUPPORT to MMC Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> [trini: Fixup some incorrect renames] Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-08 12:20:09 -06:00
CONFIG_SPL_MMC=y
serial: Rename SERIAL_SUPPORT to SERIAL Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-08-08 12:20:12 -06:00
CONFIG_SPL_SERIAL=y
Rename DRIVERS_MISC_SUPPORT to DRIVERS_MISC Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-10 21:14:31 -06:00
CONFIG_SPL_DRIVERS_MISC=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-02-17 09:58:06 -05:00
CONFIG_SPL_STACK=0x920000
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_SPL=y
CONFIG_ENV_OFFSET_REDUND=0x3E0000
Convert CONFIG_SYS_LOAD_ADDR to Kconfig Now that we have consistent usage, migrate this symbol to Kconfig. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-23 10:25:31 -04:00
CONFIG_SYS_LOAD_ADDR=0x40480000
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
CONFIG_OF_SYSTEM_SETUP=y
Convert CONFIG_USE_BOOTCOMMAND et al to Kconfig This converts the following to Kconfig: CONFIG_USE_BOOTCOMMAND CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND CONFIG_NFSBOOTCOMMAND Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-10 09:11:40 -05:00
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadimage; then run mmcboot; else run netboot; fi; fi;"
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_DEFAULT_FDT_FILE="oftree"
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2024-01-03 09:26:16 -05:00
CONFIG_SYS_CBSIZE=2048
CONFIG_SYS_PBSIZE=2074
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_BOARD_LATE_INIT=y
Convert CONFIG_SPL_BSS_START_ADDR to Kconfig This converts the following to Kconfig: CONFIG_SPL_BSS_START_ADDR Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-27 10:19:45 -04:00
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x910000
Convert CONFIG_SPL_BSS_MAX_SIZE et al to Kconfig This converts the following to Kconfig: CONFIG_SPL_BSS_MAX_SIZE CONFIG_SPL_MAX_FOOTPRINT Note that the da850evm platforms were violating the "only use one" rule here, and so now hard-code their BSS limit. Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-19 15:09:22 -04:00
CONFIG_SPL_BSS_MAX_SIZE=0x2000
Convert CONFIG_SPL_STACK to Kconfig This converts the following to Kconfig: CONFIG_SPL_STACK Signed-off-by: Tom Rini <trini@konsulko.com>
2022-05-26 13:13:21 -04:00
# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
spl: Use CONFIG_SPL... instead of CONFIG_..._SPL_... We like to put the SPL first so it is clear that it relates to SPL. Rename various malloc-related options which have crept in, to stick to this convention. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Svyatoslav Ryhel <clamor95@gmail.com>
2023-09-26 08:14:16 -06:00
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000
CONFIG_SPL_SYS_MALLOC_SIZE=0x80000
Convert CONFIG_CONS_INDEX et al to Kconfig This converts the following to Kconfig: CONFIG_CONS_INDEX CONFIG_DEBUG_UART_CLOCK CONFIG_FSL_TZPC_BP147 CONFIG_GENERIC_ATMEL_MCI CONFIG_IDENT_STRING CONFIG_LIBATA CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE CONFIG_LPC32XX_GPIO CONFIG_MP CONFIG_MPC8XXX_GPIO CONFIG_MTD_PARTITIONS CONFIG_MVGBE CONFIG_MXC_GPIO CONFIG_NR_DRAM_BANKS CONFIG_OF_BOARD_SETUP CONFIG_OF_STDOUT_VIA_ALIAS CONFIG_OF_SYSTEM_SETUP CONFIG_PREBOOT CONFIG_ROCKCHIP_SERIAL CONFIG_RTC_ENABLE_32KHZ_OUTPUT CONFIG_RTC_MV CONFIG_SCSI_AHCI CONFIG_SF_DEFAULT_BUS CONFIG_SF_DEFAULT_CS CONFIG_SF_DEFAULT_SPEED CONFIG_SOFT_SPI CONFIG_SPI_FLASH_EON CONFIG_SPI_FLASH_MACRONIX CONFIG_SPI_FLASH_MTD CONFIG_SPI_FLASH_SPANSION CONFIG_SPI_FLASH_SST CONFIG_SPI_FLASH_STMICRO CONFIG_SUPPORT_RAW_INITRD CONFIG_SYS_ARCH_TIMER CONFIG_SYS_BOARD CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE CONFIG_SYS_DCACHE_OFF CONFIG_SYS_FDT_SAVE_ADDRESS CONFIG_SYS_FLASH_CFI CONFIG_SYS_FSL_ERRATUM_ESDHC135 CONFIG_SYS_HAS_SERDES CONFIG_SYS_L2CACHE_OFF CONFIG_SYS_LITTLE_ENDIAN CONFIG_SYS_LOAD_ADDR CONFIG_SYS_MMCSD_FS_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR CONFIG_SYS_NS16550 CONFIG_SYS_PLLFIN CONFIG_SYS_SPI_U_BOOT_OFFS CONFIG_TIMER_SYS_TICK_CH CONFIG_USB_EHCI_FSL CONFIG_U_QE CONFIG_VERSION_VARIABLE Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-11 14:55:51 -05:00
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
i2c: Rename SPL/TPL_I2C_SUPPORT to I2C Rename these options so that CONFIG_IS_ENABLED can be used with them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
2021-07-10 21:14:36 -06:00
CONFIG_SPL_I2C=y
Rename SPL_POWER_SUPPORT to SPL_POWER Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-07-10 21:14:24 -06:00
CONFIG_SPL_POWER=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 11:56:52 +02:00
CONFIG_SPL_SPI_FLASH_MTD=y
Rename SPL_WATCHDOG_SUPPORT to SPL_WATCHDOG Rename this option so that CONFIG_IS_ENABLED can be used with it. Signed-off-by: Simon Glass <sjg@chromium.org>
2021-07-10 21:14:28 -06:00
CONFIG_SPL_WATCHDOG=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_HUSH_PARSER=y
configs: Resync with savedefconfig Rsync all defconfig files using moveconfig.py Signed-off-by: Tom Rini <trini@konsulko.com>
2023-10-02 10:35:27 -04:00
CONFIG_SYS_PROMPT="u-boot=> "
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
# CONFIG_CMD_CRC32 is not set
CONFIG_CMD_EEPROM=y
Convert CONFIG_SYS_I2C_EEPROM_ADDR et al to Kconfig - Rename usages of CONFIG_SYS_DEF_EEPROM_ADDR to CONFIG_SYS_I2C_EEPROM_ADDR based on current usage. - Convert CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SYS_I2C_EEPROM_BUS, CONFIG_CONFIG_SYS_EEPROM_SIZE CONFIG_SYS_EEPROM_PAGE_WRITE_BITS and CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS to Kconfig. We move these symbols around a bit and add appropriate dependencies to them. In some cases, we now add a correct default value as well. Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-17 17:59:45 -04:00
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
CONFIG_SYS_EEPROM_SIZE=4096
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
configs: phycore-imx8mm_defconfig: Enable clk command Enable clk command to dump clock tree. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 11:56:53 +02:00
CONFIG_CMD_CLK=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 11:56:52 +02:00
CONFIG_CMD_SF_TEST=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_SYS_I2C_EEPROM_ADDR=0x51
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
Convert CONFIG_FSL_USDHC to Kconfig This converts the following to Kconfig: CONFIG_FSL_USDHC Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-07 22:59:37 -05:00
CONFIG_FSL_USDHC=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 11:56:52 +02:00
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=3
CONFIG_SPI_FLASH_BAR=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_PHYLIB=y
CONFIG_PHY_TI_DP83867=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
imx: imx8m[m/p]_phycore: Enable DM_SERIAL Enable CONFIG_DM_SERIAL. uart and its pinmux was already marked with u-boot,dm-spl. Move preloader_console_init after spl_early_init to make sure driver model work. Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-06-11 20:20:58 +08:00
CONFIG_DM_SERIAL=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_MXC_UART=y
board: phytec: phycore-imx8mm: Add SPI-NOR flash support Adds SPI-NOR flash support to erase, read and write in bootloader. Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-06 11:56:52 +02:00
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_NXP_FSPI=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
phycore-imx8mm_defconfig: Enable CONFIG_IMX_TMU Enable the imx thermal driver to prevent booting when the system is too hot. Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de>
2024-02-20 11:41:44 +01:00
CONFIG_IMX_TMU=y
board: phytec: imx8mm: Add PHYTEC phyCORE-i.MX8MM support Add support PHYTEC phyCORE-i.MX8MM SOM. Supported features: - 2GB LPDDR4 RAM - 1x 1Gbit Ethernet - eMMC - external SD - debug UART3 - watchdog - i2c eeprom Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2020-08-21 09:55:53 +02:00
CONFIG_IMX_WATCHDOG=y
Reference in a new issue Copy permalink