2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2015-10-26 11:47:50 +00:00
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/*
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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* Copyright 2016-2018 NXP
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2015-10-26 11:47:50 +00:00
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* Copyright 2015, Freescale Semiconductor
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*/
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#ifndef _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
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#define _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_
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2016-09-26 15:09:24 +00:00
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#include <linux/kconfig.h>
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2015-10-26 11:47:50 +00:00
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#include <fsl_ddrc_version.h>
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2016-09-07 09:56:09 +00:00
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#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000
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2015-12-04 19:57:08 +00:00
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/*
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* Reserve secure memory
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* To be aligned with MMU block size
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*/
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2017-09-01 08:25:00 +00:00
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#define CONFIG_SYS_MEM_RESERVE_SECURE (66 * 1024 * 1024) /* 66MB */
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2017-05-15 15:52:00 +00:00
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#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
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2015-12-04 19:57:08 +00:00
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2017-03-27 18:41:01 +00:00
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#ifdef CONFIG_ARCH_LS2080A
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2015-10-26 11:47:50 +00:00
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
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#define SRDS_MAX_LANES 8
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#ifndef L1_CACHE_BYTES
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
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#endif
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2016-12-16 09:15:45 +00:00
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
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2015-10-26 11:47:50 +00:00
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/* DDR */
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2017-03-06 17:02:28 +00:00
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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2015-10-26 11:47:50 +00:00
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_IFC_LE
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2015-11-11 09:58:34 +00:00
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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2015-10-26 11:47:50 +00:00
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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2016-03-23 10:54:32 +00:00
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/* SFP */
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#define CONFIG_SYS_FSL_SFP_VER_3_4
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#define CONFIG_SYS_FSL_SFP_LE
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2016-03-23 10:54:33 +00:00
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#define CONFIG_SYS_FSL_SRK_LE
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/* Security Monitor */
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#define CONFIG_SYS_FSL_SEC_MON_LE
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2016-03-23 10:54:34 +00:00
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/* Secure Boot */
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#define CONFIG_ESBC_HDR_LS
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2016-03-23 10:54:32 +00:00
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2016-03-23 10:54:39 +00:00
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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2015-10-26 11:47:50 +00:00
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/* Cache Coherent Interconnect */
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#define CCI_MN_BASE 0x04000000
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#define CCI_MN_RNF_NODEID_LIST 0x180
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#define CCI_MN_DVM_DOMAIN_CTL 0x200
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#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
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2015-11-04 17:53:10 +00:00
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#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
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#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
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#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
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#define CCN_HN_F_SAM_NODEID_MASK 0x7f
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#define CCN_HN_F_SAM_NODEID_DDR0 0x4
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#define CCN_HN_F_SAM_NODEID_DDR1 0xe
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2015-10-26 11:47:50 +00:00
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#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
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#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
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#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
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#define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
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#define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
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#define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
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#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
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#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
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#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
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2016-01-25 06:38:45 +00:00
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#define CCI_AUX_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x0500)
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2015-10-26 11:47:50 +00:00
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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#define TZPCR0SIZE_BASE (TZPC_BASE)
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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2015-11-05 06:30:14 +00:00
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#define DCSR_CGACRE5 0x700070914ULL
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#define EPU_EPCMPR5 0x700060914ULL
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#define EPU_EPCCR5 0x700060814ULL
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#define EPU_EPSMCR5 0x700060228ULL
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#define EPU_EPECR5 0x700060314ULL
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#define EPU_EPCTR5 0x700060a14ULL
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#define EPU_EPGCR 0x700060000ULL
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2015-10-26 11:47:50 +00:00
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#define CONFIG_SYS_FSL_ERRATUM_A008751
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2015-12-16 08:45:41 +00:00
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2016-04-29 12:17:59 +00:00
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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#elif defined(CONFIG_ARCH_LS1088A)
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
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#define CONFIG_GICV3
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define SRDS_MAX_LANES 4
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2020-01-10 23:05:40 +00:00
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#define SRDS_BITS_PER_LANE 4
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armv8: ls1088a: Add NXP LS1088A SoC support
LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-31 10:42:53 +00:00
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/* TZ Protection Controller Definitions */
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#define TZPC_BASE 0x02200000
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#define TZPCR0SIZE_BASE (TZPC_BASE)
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#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
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#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
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#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
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#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
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#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
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#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
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#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06100000
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/* SMMU Defintions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* DDR */
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_IFC_LE
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* SFP */
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#define CONFIG_SYS_FSL_SFP_VER_3_4
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#define CONFIG_SYS_FSL_SFP_LE
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#define CONFIG_SYS_FSL_SRK_LE
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/* Security Monitor */
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#define CONFIG_SYS_FSL_SEC_MON_LE
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/* Secure Boot */
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#define CONFIG_ESBC_HDR_LS
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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/* LX2160A Soc Support */
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#elif defined(CONFIG_ARCH_LX2160A)
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#define TZPC_BASE 0x02200000
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#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
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2019-07-10 13:00:22 +00:00
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#if !defined(CONFIG_DM_I2C)
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_EARLY_INIT
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2019-07-10 13:00:22 +00:00
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#endif
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armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
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#define SRDS_MAX_LANES 8
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#ifndef L1_CACHE_BYTES
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#define L1_CACHE_SHIFT 6
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#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
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#endif
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
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#define CONFIG_SYS_PAGE_SIZE 0x10000
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#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
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#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
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#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
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/* DDR */
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#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
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#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_CCSR_SCFG_LE
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#define CONFIG_SYS_FSL_ESDHC_LE
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#define CONFIG_SYS_FSL_PEX_LUT_LE
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#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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/* Generic Interrupt Controller Definitions */
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#define GICD_BASE 0x06000000
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#define GICR_BASE 0x06200000
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/* SMMU Definitions */
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#define SMMU_BASE 0x05000000 /* GR0 Base */
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/* SFP */
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#define CONFIG_SYS_FSL_SFP_VER_3_4
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#define CONFIG_SYS_FSL_SFP_LE
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#define CONFIG_SYS_FSL_SRK_LE
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/* Security Monitor */
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#define CONFIG_SYS_FSL_SEC_MON_LE
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/* Secure Boot */
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#define CONFIG_ESBC_HDR_LS
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/* DCFG - GUR */
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#define CONFIG_SYS_FSL_CCSR_GUR_LE
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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|
armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
|
|
|
#elif defined(CONFIG_ARCH_LS1028A)
|
|
|
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
|
|
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|
|
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
|
|
|
|
|
#define CONFIG_GICV3
|
|
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|
|
#define CONFIG_FSL_TZPC_BP147
|
|
|
|
|
#define CONFIG_FSL_TZASC_400
|
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|
|
|
|
|
|
/* TZ Protection Controller Definitions */
|
|
|
|
|
#define TZPC_BASE 0x02200000
|
|
|
|
|
#define TZPCR0SIZE_BASE (TZPC_BASE)
|
|
|
|
|
#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
|
|
|
|
|
#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
|
|
|
|
|
#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
|
|
|
|
|
#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
|
|
|
|
|
#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
|
|
|
|
|
#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
|
|
|
|
|
#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
|
|
|
|
|
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
|
|
|
|
|
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
|
|
|
|
|
|
|
|
|
|
#define SRDS_MAX_LANES 4
|
2020-01-10 23:05:40 +00:00
|
|
|
#define SRDS_BITS_PER_LANE 4
|
armv8: ls1028a: Add NXP LS1028A SoC support
Ls1028a SoC is based on Layerscape Chassis Generation 3.2
architecture with features:
2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN
ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers,
6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc.
Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com>
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-04-10 08:43:33 +00:00
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
|
|
|
|
|
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
|
|
|
|
|
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
|
|
|
|
|
|
|
|
|
|
/* Generic Interrupt Controller Definitions */
|
|
|
|
|
#define GICD_BASE 0x06000000
|
|
|
|
|
#define GICR_BASE 0x06040000
|
|
|
|
|
|
|
|
|
|
/* SMMU Definitions */
|
|
|
|
|
#define SMMU_BASE 0x05000000 /* GR0 Base */
|
|
|
|
|
|
|
|
|
|
/* DDR */
|
|
|
|
|
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
|
|
|
|
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
|
|
|
|
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
|
|
|
|
|
#define CONFIG_SYS_FSL_ESDHC_LE
|
|
|
|
|
#define CONFIG_SYS_FSL_PEX_LUT_LE
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
|
|
|
|
|
|
|
|
|
|
/* SFP */
|
|
|
|
|
#define CONFIG_SYS_FSL_SFP_VER_3_4
|
|
|
|
|
#define CONFIG_SYS_FSL_SFP_LE
|
|
|
|
|
#define CONFIG_SYS_FSL_SRK_LE
|
|
|
|
|
|
|
|
|
|
/* SEC */
|
|
|
|
|
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
|
|
|
|
|
|
|
|
|
/* Security Monitor */
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_MON_LE
|
|
|
|
|
|
|
|
|
|
/* Secure Boot */
|
|
|
|
|
#define CONFIG_ESBC_HDR_LS
|
|
|
|
|
|
|
|
|
|
/* DCFG - GUR */
|
|
|
|
|
#define CONFIG_SYS_FSL_CCSR_GUR_LE
|
|
|
|
|
|
2016-07-05 08:01:53 +00:00
|
|
|
#elif defined(CONFIG_FSL_LSCH2)
|
2015-10-26 11:47:51 +00:00
|
|
|
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
|
2016-12-16 09:15:45 +00:00
|
|
|
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
|
|
|
|
|
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
|
2015-10-26 11:47:51 +00:00
|
|
|
|
2016-12-16 09:15:46 +00:00
|
|
|
#define DCSR_DCFG_SBEESR2 0x20140534
|
|
|
|
|
#define DCSR_DCFG_MBEESR2 0x20140544
|
|
|
|
|
|
2015-10-26 11:47:51 +00:00
|
|
|
#define CONFIG_SYS_FSL_CCSR_SCFG_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_ESDHC_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_WDOG_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_DSPI_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_QSPI_BE
|
2016-07-05 08:01:53 +00:00
|
|
|
#define CONFIG_SYS_FSL_CCSR_GUR_BE
|
2015-11-11 09:58:34 +00:00
|
|
|
#define CONFIG_SYS_FSL_PEX_LUT_BE
|
2016-07-05 08:01:53 +00:00
|
|
|
|
|
|
|
|
/* SoC related */
|
2017-03-27 18:41:02 +00:00
|
|
|
#ifdef CONFIG_ARCH_LS1043A
|
2016-07-05 08:01:53 +00:00
|
|
|
#define CONFIG_SYS_FMAN_V3
|
2018-08-27 14:33:58 +00:00
|
|
|
#define CONFIG_SYS_FSL_QMAN_V3
|
2016-07-05 08:01:53 +00:00
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 7
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 1
|
|
|
|
|
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
|
|
|
|
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
2015-10-26 11:47:51 +00:00
|
|
|
|
|
|
|
|
#define QE_MURAM_SIZE 0x6000UL
|
|
|
|
|
#define MAX_QE_RISC 1
|
|
|
|
|
#define QE_NUM_OF_SNUM 28
|
|
|
|
|
|
2016-07-05 08:01:53 +00:00
|
|
|
#define CONFIG_SYS_FSL_IFC_BE
|
2015-10-26 11:47:51 +00:00
|
|
|
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
2015-12-08 08:24:29 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_MON_BE
|
2015-10-26 11:47:51 +00:00
|
|
|
#define CONFIG_SYS_FSL_SFP_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_SRK_LE
|
|
|
|
|
#define CONFIG_KEY_REVOCATION
|
|
|
|
|
|
|
|
|
|
/* SMMU Defintions */
|
|
|
|
|
#define SMMU_BASE 0x09000000
|
|
|
|
|
|
|
|
|
|
/* Generic Interrupt Controller Definitions */
|
|
|
|
|
#define GICD_BASE 0x01401000
|
|
|
|
|
#define GICC_BASE 0x01402000
|
2017-01-17 10:31:15 +00:00
|
|
|
#define GICH_BASE 0x01404000
|
|
|
|
|
#define GICV_BASE 0x01406000
|
|
|
|
|
#define GICD_SIZE 0x1000
|
|
|
|
|
#define GICC_SIZE 0x2000
|
|
|
|
|
#define GICH_SIZE 0x2000
|
|
|
|
|
#define GICV_SIZE 0x2000
|
|
|
|
|
#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
|
|
|
|
|
#define GICD_BASE_64K 0x01410000
|
|
|
|
|
#define GICC_BASE_64K 0x01420000
|
|
|
|
|
#define GICH_BASE_64K 0x01440000
|
|
|
|
|
#define GICV_BASE_64K 0x01460000
|
|
|
|
|
#define GICD_SIZE_64K 0x10000
|
|
|
|
|
#define GICC_SIZE_64K 0x20000
|
|
|
|
|
#define GICH_SIZE_64K 0x20000
|
|
|
|
|
#define GICV_SIZE_64K 0x20000
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#define DCFG_CCSR_SVR 0x1ee00a4
|
|
|
|
|
#define REV1_0 0x10
|
|
|
|
|
#define REV1_1 0x11
|
|
|
|
|
#define GIC_ADDR_BIT 31
|
|
|
|
|
#define SCFG_GIC400_ALIGN 0x1570188
|
2015-10-26 11:47:51 +00:00
|
|
|
|
2016-04-29 12:17:59 +00:00
|
|
|
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
2016-06-03 13:11:31 +00:00
|
|
|
|
2016-12-28 16:43:40 +00:00
|
|
|
#elif defined(CONFIG_ARCH_LS1012A)
|
2016-06-03 13:11:31 +00:00
|
|
|
#define GICD_BASE 0x01401000
|
|
|
|
|
#define GICC_BASE 0x01402000
|
2017-03-23 08:18:19 +00:00
|
|
|
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
|
|
|
|
#define CONFIG_SYS_FSL_SEC_MON_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_SFP_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_SRK_LE
|
|
|
|
|
#define CONFIG_KEY_REVOCATION
|
|
|
|
|
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
2017-01-30 11:35:22 +00:00
|
|
|
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
|
|
|
|
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
|
|
|
|
|
2016-09-26 15:09:24 +00:00
|
|
|
#elif defined(CONFIG_ARCH_LS1046A)
|
2016-07-05 08:01:55 +00:00
|
|
|
#define CONFIG_SYS_FMAN_V3
|
2018-08-09 12:19:43 +00:00
|
|
|
#define CONFIG_SYS_FSL_QMAN_V3
|
2016-07-05 08:01:55 +00:00
|
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 8
|
|
|
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
|
|
|
|
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
|
|
|
|
|
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FSL_IFC_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_SFP_VER_3_2
|
2017-03-23 08:18:16 +00:00
|
|
|
#define CONFIG_SYS_FSL_SEC_MON_BE
|
2016-07-05 08:01:55 +00:00
|
|
|
#define CONFIG_SYS_FSL_SFP_BE
|
|
|
|
|
#define CONFIG_SYS_FSL_SRK_LE
|
|
|
|
|
#define CONFIG_KEY_REVOCATION
|
|
|
|
|
|
|
|
|
|
/* SMMU Defintions */
|
|
|
|
|
#define SMMU_BASE 0x09000000
|
|
|
|
|
|
|
|
|
|
/* Generic Interrupt Controller Definitions */
|
|
|
|
|
#define GICD_BASE 0x01410000
|
|
|
|
|
#define GICC_BASE 0x01420000
|
|
|
|
|
|
|
|
|
|
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
|
2015-10-26 11:47:50 +00:00
|
|
|
#else
|
|
|
|
|
#error SoC not defined
|
|
|
|
|
#endif
|
2016-07-05 08:01:53 +00:00
|
|
|
#endif
|
2015-10-26 11:47:50 +00:00
|
|
|
|
|
|
|
|
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_CONFIG_H_ */
|
