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u-boot/arch/x86/dts/chromebook_link.dts

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x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
/dts-v1/;
x86: link: Add pin configuration to the device tree At present pin configuration on link does not use the standard mechanism, but some rather ugly custom code. As a first step to resolving this, add the pin configuration to the device tree. Four of the GPIOs must be available before relocation (for SDRAM pin strapping). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:07:12 +00:00
#include <dt-bindings/gpio/x86-gpio.h>
sound: x86: link: Add sound support Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-17 03:24:57 +00:00
#include <dt-bindings/sound/azalia.h>
#include <pci_ids.h>
x86: link: Add pin configuration to the device tree At present pin configuration on link does not use the standard mechanism, but some rather ugly custom code. As a first step to resolving this, add the pin configuration to the device tree. Four of the GPIOs must be available before relocation (for SDRAM pin strapping). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:07:12 +00:00
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
/include/ "skeleton.dtsi"
x86: Add an i8042 device for boards that have it Some boards have an i8042 device. Enable the driver for all x86 boards, and add a device tree node for those which may have this keyboard. Also adjust the configuration so that i8042 is always separate from the VGA, and rename the stdin driver accordingly. With this commit the keyboard will not work, but it is fixed in the next commit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-11 17:05:43 +00:00
/include/ "keyboard.dtsi"
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
/include/ "serial.dtsi"
x86: Switch to use DM sysreset driver This converts all x86 boards over to DM sysreset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2018-07-19 10:07:33 +00:00
/include/ "reset.dtsi"
x86: Enable DM RTC support for all x86 boards Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> (Squashed in 'x86: Fix RTC build error on ivybridge')
2015-07-15 08:23:39 +00:00
/include/ "rtc.dtsi"
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
x86: dts: Define a default TSC timer frequency If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-28 04:00:23 +00:00
#include "tsc_timer.dtsi"
x86: Provide default SMBIOS manufacturer/product Add a file containing defaults for these, using the existing CONFIG options. This file must be included with #include since it needs to be passed through the C preprocessor. Enable the driver for all x86 boards that generate SMBIOS tables. Disable it for coral since it has its own driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: reword the commit message a little bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-11-05 13:32:17 +00:00
#include "smbios.dtsi"
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
/ {
model = "Google Link";
compatible = "google,link", "intel,celeron-ivybridge";
x86: dts: Add SPI flash MRC details for chromebook_link Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-20 05:16:13 +00:00
aliases {
x86: Correct spi node alias With recent changes spi node was moved to a place as a subnode under pch, so update the alias to refer to its correct place as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-27 08:56:34 +00:00
spi0 = &spi;
x86: ivybridge: Drop special EHCI init This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:55 +00:00
usb0 = &usb_0;
usb1 = &usb_1;
x86: dts: Add SPI flash MRC details for chromebook_link Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-20 05:16:13 +00:00
};
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
config {
silent_console = <0>;
};
x86: ivybridge: Use common CPU init code The existing ivybridge code predates the normal multi-core CPU init, and it is not used. Remove it and add CPU nodes to the device tree so that all four CPUs are set up. Also enable the 'cpu' command. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:23 +00:00
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <0>;
intel,apic-id = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <1>;
intel,apic-id = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <2>;
intel,apic-id = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "intel,core-gen3";
reg = <3>;
intel,apic-id = <3>;
};
};
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
chosen {
stdout-path = "/serial";
};
x86: Add an i8042 device for boards that have it Some boards have an i8042 device. Enable the driver for all x86 boards, and add a device tree node for those which may have this keyboard. Also adjust the configuration so that i8042 is always separate from the VGA, and rename the stdin driver accordingly. With this commit the keyboard will not work, but it is fixed in the next commit. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2015-11-11 17:05:43 +00:00
keyboard {
intel,duplicate-por;
};
x86: link: Add pin configuration to the device tree At present pin configuration on link does not use the standard mechanism, but some rather ugly custom code. As a first step to resolving this, add the pin configuration to the device tree. Four of the GPIOs must be available before relocation (for SDRAM pin strapping). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-12 05:07:12 +00:00
pch_pinctrl {
compatible = "intel,x86-pinctrl";
u-boot,dm-pre-reloc;
reg = <0 0>;
gpio_a0 {
gpio-offset = <0 0>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_a1 {
gpio-offset = <0>;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <1>;
};
gpio_a3 {
gpio-offset = <0 3>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_a5 {
gpio-offset = <0 5>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_a6 {
gpio-offset = <0 6>;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <1>;
};
gpio_a7 {
gpio-offset = <0 7>;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_a8 {
gpio-offset = <0 8>;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_a9 {
gpio-offset = <0 9>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_a10 {
u-boot,dm-pre-reloc;
gpio-offset = <0 10>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_a11 {
gpio-offset = <0 11>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_a12 {
gpio-offset = <0 12>;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_a14 {
gpio-offset = <0 14>;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_a15 {
gpio-offset = <0 15>;
mode-gpio;
direction = <PIN_INPUT>;
invert;
};
gpio_a21 {
gpio-offset = <0 21>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_a24 {
gpio-offset = <0 24>;
mode-gpio;
output-value = <0>;
direction = <PIN_OUTPUT>;
};
gpio_a28 {
gpio-offset = <0 28>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b4 {
gpio-offset = <0x30 4>;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <1>;
};
gpio_b9 {
u-boot,dm-pre-reloc;
gpio-offset = <0x30 9>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b10 {
u-boot,dm-pre-reloc;
gpio-offset = <0x30 10>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b11 {
u-boot,dm-pre-reloc;
gpio-offset = <0x30 11>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b25 {
gpio-offset = <0x30 25>;
mode-gpio;
direction = <PIN_INPUT>;
};
gpio_b28 {
gpio-offset = <0x30 28>;
mode-gpio;
direction = <PIN_OUTPUT>;
output-value = <1>;
};
};
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
pci {
x86: ivybridge: Drop the special PCI driver There is nothing special about the ivybridge pci driver now, so just use the generic one. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:41 +00:00
compatible = "pci-x86";
dm: x86: pci: Convert coreboot to use driver model for pci Move coreboot-x86 over to driver model for PCI. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-05 19:25:32 +00:00
#address-cells = <3>;
#size-cells = <2>;
u-boot,dm-pre-reloc;
ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
0x01000000 0x0 0x1000 0x1000 0 0xefff>;
x86: ivybridge: Add a driver for the bd82x6x northbridge Add a driver with an empty probe function where we can move init code in follow-on patches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:15 +00:00
northbridge@0,0 {
reg = <0x00000000 0 0 0 0>;
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: ivybridge: Add a driver for the bd82x6x northbridge Add a driver with an empty probe function where we can move init code in follow-on patches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:15 +00:00
compatible = "intel,bd82x6x-northbridge";
x86: dts: link: Add board ID GPIOs At present the board ID GPIOs are hard-coded. Move them to the device tree so that we can use general SDRAM init code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:12 +00:00
board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
<&gpio_b 11 0>, <&gpio_a 10 0>;
x86: dts: link: Move SPD info into the memory controller The SDRAM SPD (Serial Presence Detect) information should be contained with the SDRAM controller. This makes it easier for the controller to access it and removes the need for a separate compatible string. As a first step, move the information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:11 +00:00
spd {
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: dts: link: Move SPD info into the memory controller The SDRAM SPD (Serial Presence Detect) information should be contained with the SDRAM controller. This makes it easier for the controller to access it and removes the need for a separate compatible string. As a first step, move the information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:11 +00:00
#address-cells = <1>;
#size-cells = <0>;
elpida_4Gb_1600_x16 {
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: dts: link: Move SPD info into the memory controller The SDRAM SPD (Serial Presence Detect) information should be contained with the SDRAM controller. This makes it easier for the controller to access it and removes the need for a separate compatible string. As a first step, move the information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:11 +00:00
reg = <0>;
data = [92 10 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 81
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 42 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 02 fe 00
11 52 00 00 00 07 7f 37
45 42 4a 32 30 55 47 36
45 42 55 30 2d 47 4e 2d
46 20 30 20 02 fe 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
samsung_4Gb_1600_1.35v_x16 {
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: dts: link: Move SPD info into the memory controller The SDRAM SPD (Serial Presence Detect) information should be contained with the SDRAM controller. This makes it easier for the controller to access it and removes the need for a separate compatible string. As a first step, move the information. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:11 +00:00
reg = <1>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
f0 0a 3c 3c 01 40 83 01
00 80 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 11 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 ce 01
00 00 00 00 00 00 6a 04
4d 34 37 31 42 35 36 37
34 42 48 30 2d 59 4b 30
20 20 00 00 80 ce 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00];
};
micron_4Gb_1600_1.35v_x16 {
reg = <2>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
69 78 69 3c 69 11 18 81
20 08 3c 3c 01 40 83 05
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 0f 01 02 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 80 2c 00
00 00 00 00 00 00 ad 75
34 4b 54 46 32 35 36 36
34 48 5a 2d 31 47 36 45
31 20 45 31 80 2c 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff
ff ff ff ff ff ff ff ff];
};
};
x86: ivybridge: Add a driver for the bd82x6x northbridge Add a driver with an empty probe function where we can move init code in follow-on patches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:15 +00:00
};
x86: ivybridge: Use syscon for the GMA device Until we have a proper video uclass we can use syscon to handle the GMA device, and avoid the special device tree and PCI searching. Update the code to work this way. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:59 +00:00
gma@2,0 {
reg = <0x00001000 0 0 0 0>;
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
compatible = "intel,gma";
intel,dp_hotplug = <0 0 0x06>;
intel,panel-port-select = <1>;
intel,panel-power-cycle-delay = <6>;
intel,panel-power-up-delay = <2000>;
intel,panel-power-down-delay = <500>;
intel,panel-power-backlight-on-delay = <2000>;
intel,panel-power-backlight-off-delay = <2000>;
intel,cpu-backlight = <0x00000200>;
intel,pch-backlight = <0x04000000>;
};
x86: ivybridge: Convert SDRAM init to use driver model SDRAM init needs access to the Northbridge controller and the Intel Management Engine device. Add the latter to the device tree and convert all of this code to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:50 +00:00
me@16,0 {
reg = <0x0000b000 0 0 0 0>;
compatible = "intel,me";
u-boot,dm-pre-reloc;
};
x86: ivybridge: Drop special EHCI init This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:55 +00:00
usb_1: usb@1a,0 {
reg = <0x0000d000 0 0 0 0>;
compatible = "ehci-pci";
};
sound: x86: link: Add sound support Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-17 03:24:57 +00:00
hda@1b,0 {
reg = <0x0000d800 0 0 0 0>;
compatible = "intel,bd82x6x-hda";
/* These correspond to the Intel HDA specification */
beep-verbs = <
0x00170500 /* power up codec */
0x00270500 /* power up DAC */
0x00b70500 /* power up speaker */
0x00b70740 /* enable speaker out */
0x00b78d00 /* enable EAPD pin */
0x00b70c02 /* set EAPD pin */
0x0143b013>; /* beep volume */
codecs {
creative_codec: creative-ca0132 {
vendor-id = <PCI_VENDOR_ID_CREATIVE>;
device-id = <PCI_DEVICE_ID_CREATIVE_CA01322>;
};
intel_hdmi: hdmi {
vendor-id = <PCI_VENDOR_ID_INTEL>;
device-id = <PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI>;
};
};
};
x86: ivybridge: Drop special EHCI init This is not needed. On reset wake-on-disconnect is already set. It may a problem during a soft reset or resume, but for now it does not seem important. Also drop the command register update since PCI auto-config does it for us. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:55 +00:00
usb_0: usb@1d,0 {
reg = <0x0000e800 0 0 0 0>;
compatible = "ehci-pci";
};
dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:21 +00:00
pch@1f,0 {
dm: x86: pci: Convert chromebook_link to use driver model for pci Move chromebook_link over to driver model for PCI. This involves: - adding a uclass for platform controller hub - removing most of the existing PCI driver - adjusting how CPU init works to use driver model instead - rename the lpc compatible string (it will be removed later) This does not really take advantage of driver model fully, but it does work. Furture work will improve the code structure to remove many of the explicit calls to init the board. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-05 19:25:33 +00:00
reg = <0x0000f800 0 0 0 0>;
dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:21 +00:00
compatible = "intel,bd82x6x", "intel,pch9";
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
u-boot,dm-pre-reloc;
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
#address-cells = <1>;
#size-cells = <1>;
intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
0x80 0x80 0x80 0x80>;
intel,gpi-routing = <0 0 0 0 0 0 0 2
1 0 0 0 0 0 0 0>;
/* Enable EC SMI source */
intel,alt-gp-smi-enable = <0x0100>;
dm: x86: spi: Convert ICH SPI driver to driver model PCI API At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-19 03:19:21 +00:00
x86: Correct spi node alias With recent changes spi node was moved to a place as a subnode under pch, so update the alias to refer to its correct place as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2016-01-27 08:56:34 +00:00
spi: spi {
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
#address-cells = <1>;
#size-cells = <0>;
spi: ich: Use compatible strings to distinguish controller version At present ich spi driver gets the controller version information via pch, but this can be simply retrieved via spi node's compatible string. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jteki@openedev.com> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:37 +00:00
compatible = "intel,ich9-spi";
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
reg = <0>;
x86: dts: Add "m25p,fast-read" to SPI flash node Except ICH7 SPI, all SPI flashes connected to ICH9 / Fast SPI should have "m25p,fast-read" property present in their DT nodes. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
2021-07-29 12:18:23 +00:00
m25p,fast-read;
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
compatible = "winbond,w25q64",
x86: dts: switch spi-flash to jedec, spi-nor compatible The x86 code and DT uses "spi-flash" to detect a flash node, switch to "jedec,spi-nor" in the DTS files and in fdtdec by switching the GENERIC_SPI_FLASH value to to jedec,spi-nor. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
2019-02-10 10:16:21 +00:00
"jedec,spi-nor";
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
memory-map = <0xff800000 0x00800000>;
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
};
};
};
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
x86: link: Add required GPIO properties In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:10 +00:00
gpio_a: gpioa {
x86: ich6_gpio: Convert to use proper DM API At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:47 +00:00
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
x86: link: Add required GPIO properties In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:10 +00:00
#gpio-cells = <2>;
gpio-controller;
x86: ich6_gpio: Convert to use proper DM API At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:47 +00:00
reg = <0 0x10>;
bank-name = "A";
};
x86: link: Add required GPIO properties In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:10 +00:00
gpio_b: gpiob {
x86: ich6_gpio: Convert to use proper DM API At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:47 +00:00
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
x86: link: Add required GPIO properties In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:10 +00:00
#gpio-cells = <2>;
gpio-controller;
x86: ich6_gpio: Convert to use proper DM API At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:47 +00:00
reg = <0x30 0x10>;
bank-name = "B";
};
x86: link: Add required GPIO properties In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:10 +00:00
gpio_c: gpioc {
x86: ich6_gpio: Convert to use proper DM API At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:47 +00:00
compatible = "intel,ich6-gpio";
u-boot,dm-pre-reloc;
x86: link: Add required GPIO properties In order to use GPIO phandles we need to add some GPIO properties as specified by the GPIO bindings. Add these for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-03-07 02:28:10 +00:00
#gpio-cells = <2>;
gpio-controller;
x86: ich6_gpio: Convert to use proper DM API At present this GPIO driver still uses the legacy PCI API. Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has nodes for the GPIO peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the PCH device. Update the device tree files to show the GPIO controller within the PCH, so that PCI access works as expected. This also adds '#address-cells' and '#size-cells' to the PCH node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
2016-02-01 09:40:47 +00:00
reg = <0x40 0x10>;
bank-name = "C";
};
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
lpc {
compatible = "intel,bd82x6x-lpc";
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
#address-cells = <1>;
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
#size-cells = <0>;
x86: ivybridge: Set up the LPC device using driver model Find the LPC device in arch_cpu_init_dm() as a first step to converting this code to use driver model. Probing the LPC will probe its parent (the PCH) automatically, so make sure that probing the PCH does nothing before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:10 +00:00
u-boot,dm-pre-reloc;
x86: ivybridge: Move lpc_early_init() to probe() Move this code to the LPC's probe() method so that it will happen automatically when the LPC is probed before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:11 +00:00
intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
x86: chromebook_link: dts: Add PCH and LPC devices The PCH (Platform Controller Hub) is on the PCI bus, so show it as such. The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the right place also. Rename the compatible strings to be more descriptive since this board is the only user. Once we are using driver model fully on x86, these will be dropped. Signed-off-by: Simon Glass <sjg@chromium.org>
2015-03-26 15:29:29 +00:00
cros-ec@200 {
compatible = "google,cros-ec";
reg = <0x204 1 0x200 1 0x880 0x80>;
/*
* Describes the flash memory within
* the EC
*/
#address-cells = <1>;
#size-cells = <1>;
flash@8000000 {
reg = <0x08000000 0x20000>;
erase-value = <0xff>;
};
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
};
};
};
x86: ivybridge: Do the SATA init before relocation The SATA device needs to set itself up so that it appears correctly on the PCI bus. The easiest way to do this is to set it up to probe before relocation. This can do the early setup. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:35 +00:00
sata@1f,2 {
compatible = "intel,pantherpoint-ahci";
reg = <0x0000fa00 0 0 0 0>;
u-boot,dm-pre-reloc;
intel,sata-mode = "ahci";
intel,sata-port-map = <1>;
intel,sata-port0-gen3-tx = <0x00880a7f>;
};
x86: ivybridge: Use the I2C driver to perform SMbus init Move the init code into the I2C driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2016-01-17 23:11:45 +00:00
smbus: smbus@1f,3 {
compatible = "intel,ich-i2c";
reg = <0x0000fb00 0 0 0 0>;
u-boot,dm-pre-reloc;
};
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
};
exynos: x86: dts: Add tpm nodes to the device tree for Chrome OS devices Add a TPM node to the various Chromebooks so that driver can be converted to driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Christophe Ricard<christophe-h.ricard@st.com> Reviewed-by: Heiko Schocher <hs@denx.de>
2015-08-23 00:31:37 +00:00
tpm {
reg = <0xfed40000 0x5000>;
compatible = "infineon,slb9635lpc";
};
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
microcode {
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
update@0 {
x86: link: Set up device tree for SPL Add the correct pre-relocation tag so that the required device tree nodes are present in the SPL device tree. On x86 it doesn't make a lot of sense to have a separate SPL device tree. Since everything is in the same ROM we might as well just use the main device tree in both SPL and U-Boot proper. But we haven't implemented that, so this is a good first step. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 14:04:24 +00:00
u-boot,dm-pre-reloc;
x86: Make chromebook_link the default board for coreboot Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link which is currently the only real board officially supported to run U-Boot loaded by coreboot. Note the symbolic link file chromebook_link.dts is deleted and link.dts is renamed to chromebook_link.dts. To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86 define needs to be moved to arch/x86/cpu/ivybridge/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
2015-01-06 14:14:21 +00:00
#include "microcode/m12306a9_0000001b.dtsi"
};
};
};
sound: x86: link: Add sound support Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-02-17 03:24:57 +00:00
&creative_codec {
verbs = <
/**
* Malcolm Setup. These correspond to the Intel HDA
* specification.
*/
0x01570d09 0x01570c23 0x01570a01 0x01570df0
0x01570efe 0x01570775 0x015707d3 0x01570709
0x01570753 0x015707d4 0x015707ef 0x01570775
0x015707d3 0x01570709 0x01570702 0x01570737
0x01570778 0x01553cce 0x015575c9 0x01553dce
0x0155b7c9 0x01570de8 0x01570efe 0x01570702
0x01570768 0x01570762 0x01553ace 0x015546c9
0x01553bce 0x0155e8c9 0x01570d49 0x01570c88
0x01570d20 0x01570e19 0x01570700 0x01571a05
0x01571b29 0x01571a04 0x01571b29 0x01570a01
/* Pin Widget Verb Table */
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144dc0c2 */
AZALIA_SUBVENDOR(0x0, 0x144dc0c2)
/*
* Pin Complex (NID 0x0B) Port-G Analog Unknown
* Speaker at Int N/A
*/
AZALIA_PIN_CFG(0x0, 0x0b, 0x901700f0)
/* Pin Complex (NID 0x0C) N/C */
AZALIA_PIN_CFG(0x0, 0x0c, 0x70f000f0)
/* Pin Complex (NID 0x0D) N/C */
AZALIA_PIN_CFG(0x0, 0x0d, 0x70f000f0)
/* Pin Complex (NID 0x0E) N/C */
AZALIA_PIN_CFG(0x0, 0x0e, 0x70f000f0)
/* Pin Complex (NID 0x0F) N/C */
AZALIA_PIN_CFG(0x0, 0x0f, 0x70f000f0)
/* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */
AZALIA_PIN_CFG(0x0, 0x10, 0x032110f0)
/* Pin Complex (NID 0x11) Port-B Click Mic */
AZALIA_PIN_CFG(0x0, 0x11, 0x90a700f0)
/* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */
AZALIA_PIN_CFG(0x0, 0x12, 0x03a110f0)
/* Pin Complex (NID 0x13) What you hear */
AZALIA_PIN_CFG(0x0, 0x13, 0x90d600f0)>;
};
&intel_hdmi {
verbs = <
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
AZALIA_SUBVENDOR(0x3, 0x80860101)
/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
AZALIA_PIN_CFG(0x3, 0x05, 0x18560010)
/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
AZALIA_PIN_CFG(0x3, 0x06, 0x18560020)
/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)>;
};
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