u-boot/drivers/misc/Kconfig

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#
# Multifunction miscellaneous devices
#
menu "Multifunction device drivers"
config MISC
bool "Enable Driver Model for Misc drivers"
depends on DM
help
Enable driver model for miscellaneous devices. This class is
used only for those do not fit other more general classes. A
set of generic read, write and ioctl methods may be used to
access the device.
config SPL_MISC
bool "Enable Driver Model for Misc drivers in SPL"
depends on SPL_DM
default MISC
help
Enable driver model for miscellaneous devices. This class is
used only for those do not fit other more general classes. A
set of generic read, write and ioctl methods may be used to
access the device.
config TPL_MISC
bool "Enable Driver Model for Misc drivers in TPL"
depends on TPL_DM
default MISC
help
Enable driver model for miscellaneous devices. This class is
used only for those do not fit other more general classes. A
set of generic read, write and ioctl methods may be used to
access the device.
config VPL_MISC
bool "Enable Driver Model for Misc drivers in VPL"
depends on VPL_DM
default MISC
help
Enable driver model for miscellaneous devices. This class is
used only for those do not fit other more general classes. A
set of generic read, write and ioctl methods may be used to
access the device.
misc: Add support for nvmem cells This adds support for "nvmem cells" as seen in Linux. The nvmem device class in Linux is used for various assorted ROMs and EEPROMs. In this sense, it is similar to UCLASS_MISC, but also includes UCLASS_I2C_EEPROM, UCLASS_RTC, and UCLASS_MTD. New drivers corresponding to a Linux-style nvmem device should be implemented as one of the previously-mentioned uclasses. The nvmem API acts as a compatibility layer to adapt the (slightly different) APIs of these uclasses. It also handles the lookup of nvmem cells. While nvmem devices can be accessed directly, they are most often used by reading/writing contiguous values called "cells". Cells typically hold information like calibration, versions, or configuration (such as mac addresses). nvmem devices can specify "cells" in their device tree: qfprom: eeprom@700000 { #address-cells = <1>; #size-cells = <1>; reg = <0x00700000 0x100000>; /* ... */ tsens_calibration: calib@404 { reg = <0x404 0x10>; }; }; which can then be referenced like: tsens { /* ... */ nvmem-cells = <&tsens_calibration>; nvmem-cell-names = "calibration"; }; The tsens driver could then read the calibration value like: struct nvmem_cell cal_cell; u8 cal[16]; nvmem_cell_get_by_name(dev, "calibration", &cal_cell); nvmem_cell_read(&cal_cell, cal, sizeof(cal)); Because nvmem devices are not all of the same uclass, supported uclasses must register a nvmem_interface struct. This allows CONFIG_NVMEM to be enabled without depending on specific uclasses. At the moment, nvmem_interface is very bare-bones, and assumes that no initialization is necessary. However, this could be amended in the future. Although I2C_EEPROM and MISC are quite similar (and could likely be unified), they present different read/write function signatures. To abstract over this, NVMEM uses the same read/write signature as Linux. In particular, short read/writes are not allowed, which is allowed by MISC. The functionality implemented by nvmem cells is very similar to that provided by i2c_eeprom_partition. "fixed-partition"s for eeproms does not seem to have made its way into Linux or into any device tree other than sandbox. It is possible that with the introduction of this API it would be possible to remove it. Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-05-05 17:11:39 +00:00
config NVMEM
bool "NVMEM support"
help
This adds support for a common interface to different types of
non-volatile memory. Consumers can use nvmem-cells properties to look
up hardware configuration data such as MAC addresses and calibration
settings.
config SPL_NVMEM
bool "NVMEM support in SPL"
help
This adds support for a common interface to different types of
non-volatile memory. Consumers can use nvmem-cells properties to look
up hardware configuration data such as MAC addresses and calibration
settings.
config ALTERA_SYSID
bool "Altera Sysid support"
depends on MISC
help
Select this to enable a sysid for Altera devices. Please find
details on the "Embedded Peripherals IP User Guide" of Altera.
config ATSHA204A
bool "Support for Atmel ATSHA204A module"
select BITREVERSE
depends on MISC
help
Enable support for I2C connected Atmel's ATSHA204A
CryptoAuthentication module found for example on the Turris Omnia
board.
config GATEWORKS_SC
bool "Gateworks System Controller Support"
depends on MISC
help
Enable access for the Gateworks System Controller used on Gateworks
boards to provide a boot watchdog, power control, temperature monitor,
voltage ADCs, and EEPROM.
config ROCKCHIP_EFUSE
bool "Rockchip e-fuse support"
depends on MISC
help
Enable (read-only) access for the e-fuse block found in Rockchip
SoCs: accesses can either be made using byte addressing and a length
or through child-nodes that are generated based on the e-fuse map
retrieved from the DTS.
config ROCKCHIP_OTP
bool "Rockchip OTP Support"
depends on MISC
help
Enable (read-only) access for the one-time-programmable memory block
found in Rockchip SoCs: accesses can either be made using byte
addressing and a length or through child-nodes that are generated
based on the e-fuse map retrieved from the DTS.
config SIFIVE_OTP
bool "SiFive eMemory OTP driver"
depends on MISC
help
Enable support for reading and writing the eMemory OTP on the
SiFive SoCs.
config SMSC_LPC47M
bool "LPC47M SMSC driver"
config SMSC_SIO1007
bool "SIO1007 SMSC driver"
config VEXPRESS_CONFIG
bool "Enable support for Arm Versatile Express config bus"
depends on MISC
help
If you say Y here, you will get support for accessing the
configuration bus on the Arm Versatile Express boards via
a sysreg driver.
config CMD_CROS_EC
bool "Enable crosec command"
depends on CROS_EC
help
Enable command-line access to the Chrome OS EC (Embedded
Controller). This provides the 'crosec' command which has
a number of sub-commands for performing EC tasks such as
updating its flash, accessing a small saved context area
and talking to the I2C bus behind the EC (if there is one).
config CROS_EC
bool "Enable Chrome OS EC"
help
Enable access to the Chrome OS EC. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
provides access to the keyboard, some internal storage and may
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
config SPL_CROS_EC
bool "Enable Chrome OS EC in SPL"
depends on SPL_MISC
help
Enable access to the Chrome OS EC in SPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
provides access to the keyboard, some internal storage and may
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
config TPL_CROS_EC
bool "Enable Chrome OS EC in TPL"
depends on TPL_MISC
help
Enable access to the Chrome OS EC in TPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
provides access to the keyboard, some internal storage and may
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
config VPL_CROS_EC
bool "Enable Chrome OS EC in VPL"
depends on VPL_MISC
help
Enable access to the Chrome OS EC in VPL. This is a separate
microcontroller typically available on a SPI bus on Chromebooks. It
provides access to the keyboard, some internal storage and may
control access to the battery and main PMIC depending on the
device. You can use the 'crosec' command to access it.
config CROS_EC_I2C
bool "Enable Chrome OS EC I2C driver"
depends on CROS_EC
help
Enable I2C access to the Chrome OS EC. This is used on older
ARM Chromebooks such as snow and spring before the standard bus
changed to SPI. The EC will accept commands across the I2C using
a special message protocol, and provide responses.
config CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver"
depends on CROS_EC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
config SPL_CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver in SPL"
depends on CROS_EC && SPL_MISC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
config TPL_CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver in TPL"
depends on CROS_EC && TPL_MISC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
config VPL_CROS_EC_LPC
bool "Enable Chrome OS EC LPC driver in VPL"
depends on CROS_EC && VPL_MISC
help
Enable I2C access to the Chrome OS EC. This is used on x86
Chromebooks such as link and falco. The keyboard is provided
through a legacy port interface, so on x86 machines the main
function of the EC is power and thermal management.
config CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver"
depends on CROS_EC && SANDBOX
help
Enable a sandbox emulation of the Chrome OS EC. This supports
keyboard (use the -l flag to enable the LCD), verified boot context,
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
config SPL_CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver in SPL"
depends on SPL_CROS_EC && SANDBOX
help
Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
keyboard (use the -l flag to enable the LCD), verified boot context,
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
config TPL_CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver in TPL"
depends on TPL_CROS_EC && SANDBOX
help
Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
keyboard (use the -l flag to enable the LCD), verified boot context,
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
config VPL_CROS_EC_SANDBOX
bool "Enable Chrome OS EC sandbox driver in VPL"
depends on VPL_CROS_EC && SANDBOX
help
Enable a sandbox emulation of the Chrome OS EC in VPL. This supports
keyboard (use the -l flag to enable the LCD), verified boot context,
EC flash read/write/erase support and a few other things. It is
enough to perform a Chrome OS verified boot on sandbox.
config CROS_EC_SPI
bool "Enable Chrome OS EC SPI driver"
depends on CROS_EC
help
Enable SPI access to the Chrome OS EC. This is used on newer
ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
provides a faster and more robust interface than I2C but the bugs
are less interesting.
config DS4510
bool "Enable support for DS4510 CPU supervisor"
help
Enable support for the Maxim DS4510 CPU supervisor. It has an
integrated 64-byte EEPROM, four programmable non-volatile I/O pins
and a configurable timer for the supervisor function. The device is
connected over I2C.
config FSL_IIM
bool "Enable FSL IC Identification Module (IIM) driver"
depends on ARCH_MX31 || ARCH_MX5
config FSL_SEC_MON
bool "Enable FSL SEC_MON Driver"
help
Freescale Security Monitor block is responsible for monitoring
system states.
Security Monitor can be transitioned on any security failures,
like software violations or hardware security violations.
choice
prompt "Security monitor interaction endianess"
depends on FSL_SEC_MON
default SYS_FSL_SEC_MON_BE if PPC
default SYS_FSL_SEC_MON_LE
config SYS_FSL_SEC_MON_LE
bool "Security monitor interactions are little endian"
config SYS_FSL_SEC_MON_BE
bool "Security monitor interactions are big endian"
endchoice
config IRQ
bool "Interrupt controller"
help
This enables support for interrupt controllers, including ITSS.
Some devices have extra features, such as Apollo Lake. The
device has its own uclass since there are several operations
involved.
config JZ4780_EFUSE
bool "Ingenic JZ4780 eFUSE support"
depends on ARCH_JZ47XX
help
This selects support for the eFUSE on Ingenic JZ4780 SoCs.
arm: layerscape: Add sfp driver This adds a driver for the Security Fuse Processor (SFP) present on LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and other "security" related fuses. Similar devices (sharing the same name) are present on other processors, but for the moment this just supports the LS2 variants. The mirror registers are loaded during power-on reset. All mirror registers must be programmed or read at once. Because of this, `fuse prog` will program all fuses, even though only one might be specified. To prevent accidentally burning through all your fuse programming cycles with something like `fuse prog 0 0 A B C D`, we limit ourselves to one programming cycle per reset. Fuses are numbered based on their address. The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc. The TA_PROG_SFP supply must be enabled when programming fuses, but must be disabled when reading them. Typically this supply is enabled by inserting a jumper or by setting a register in the board's FPGA. I've also added support for using a regulator. This could be helpful for automatically issuing the FPGA write, or for toggling a GPIO controlling the supply. I suggest using the following procedure for programming: 1. Override the fuses you wish to program => fuse override 0 2 A B C D 2. Inspect the values and ensure that they are what you expect => fuse sense 0 2 4 3. Enable TA_PROG_SFP 4. Issue a program command using OSPR0 as a dummy. Since it contains the write-protect bit you will usually want to write it last anyway. => fuse prog 0 0 0 5. Disable TA_PROG_SFP 6. Read back the fuses and ensure they are correct => fuse read 0 2 4 Signed-off-by: Sean Anderson <sean.anderson@seco.com>
2022-04-22 18:34:18 +00:00
config LS2_SFP
bool "Layerscape Security Fuse Processor"
depends on FSL_LSCH2 || ARCH_LS1021A
depends on MISC
imply DM_REGULATOR
help
This adds support for the Security Fuse Processor found on Layerscape
SoCs. It contains various fuses related to secure boot, including the
Super Root Key hash, One-Time-Programmable Master Key, Debug
Challenge/Response values, and others. Fuses are numbered according
to their four-byte offset from the start of the bank.
If you don't need to read/program fuses, say 'n'.
config MXC_OCOTP
bool "Enable MXC OCOTP Driver"
depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
default y
help
If you say Y here, you will get support for the One Time
Programmable memory pages that are stored on the some
Freescale i.MX processors.
config MXS_OCOTP
bool "Enable MXS OCOTP Driver"
depends on ARCH_MX23 || ARCH_MX28
help
If you say Y here, you will get support for the One Time
Programmable memory pages that are stored on the
Freescale i.MXS family of processors.
config NPCM_HOST
bool "Enable support espi or LPC for Host"
depends on REGMAP && SYSCON
help
Enable NPCM BMC espi or LPC support for Host reading and writing.
config SPL_MXC_OCOTP
bool "Enable MXC OCOTP driver in SPL"
depends on SPL_DRIVERS_MISC && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
default y
help
If you say Y here, you will get support for the One Time
Programmable memory pages, that are stored on some
Freescale i.MX processors, in SPL.
config NPCM_OTP
bool "Nnvoton NPCM BMC On-Chip OTP Memory Support"
depends on (ARM && ARCH_NPCM)
default n
help
Support NPCM BMC OTP memory (fuse).
To compile this driver as a module, choose M here: the module
will be called npcm_otp.
config IMX_SENTINEL
bool "Enable i.MX Sentinel MU driver and API"
depends on MISC && (ARCH_IMX9 || ARCH_IMX8ULP)
help
If you say Y here to enable Message Unit driver to work with
Sentinel core on some NXP i.MX processors.
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help
If you say Y here, you will get support for the Nuvoton
NCT6102D Super I/O driver. This can be used to enable or
disable the legacy UART, the watchdog or other devices
in the Nuvoton Super IO chips on X86 platforms.
config P2SB
bool "Intel Primary to Sideband Bridge"
depends on X86 || SANDBOX
help
This enables support for the Intel Primary to Sideband Bridge,
abbreviated to P2SB. The P2SB is used to access various peripherals
such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
space. The space is segmented into different channels and peripherals
are accessed by device-specific means within those channels. Devices
should be added in the device tree as subnodes of the P2SB. A
Peripheral Channel Register? (PCR) API is provided to access those
devices - see pcr_readl(), etc.
config SPL_P2SB
bool "Intel Primary to Sideband Bridge in SPL"
depends on SPL_MISC && (X86 || SANDBOX)
help
The Primary to Sideband Bridge is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added
in the device tree as subnodes of the p2sb.
config TPL_P2SB
bool "Intel Primary to Sideband Bridge in TPL"
depends on TPL_MISC && (X86 || SANDBOX)
help
The Primary to Sideband Bridge is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added
in the device tree as subnodes of the p2sb.
config PWRSEQ
bool "Enable power-sequencing drivers"
depends on DM
help
Power-sequencing drivers provide support for controlling power for
devices. They are typically referenced by a phandle from another
device. When the device is started up, its power sequence can be
initiated.
config SPL_PWRSEQ
bool "Enable power-sequencing drivers for SPL"
depends on SPL_MISC && PWRSEQ
help
Power-sequencing drivers provide support for controlling power for
devices. They are typically referenced by a phandle from another
device. When the device is started up, its power sequence can be
initiated.
config PCA9551_LED
bool "Enable PCA9551 LED driver"
help
Enable driver for PCA9551 LED controller. This controller
is connected via I2C. So I2C needs to be enabled.
config PCA9551_I2C_ADDR
hex "I2C address of PCA9551 LED controller"
depends on PCA9551_LED
default 0x60
help
The I2C address of the PCA9551 LED controller.
config STM32MP_FUSE
bool "Enable STM32MP fuse wrapper providing the fuse API"
depends on ARCH_STM32MP && MISC
default y if CMD_FUSE
help
If you say Y here, you will get support for the fuse API (OTP)
for STM32MP architecture.
This API is needed for CMD_FUSE.
config STM32_RCC
bool "Enable RCC driver for the STM32 SoC's family"
depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
help
Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
block) is responsible of the management of the clock and reset
generation.
This driver is similar to an MFD driver in the Linux kernel.
config TEGRA_CAR
bool "Enable support for the Tegra CAR driver"
depends on TEGRA_NO_BPMP
help
The Tegra CAR (Clock and Reset Controller) is a HW module that
controls almost all clocks and resets in a Tegra SoC.
config TEGRA186_BPMP
bool "Enable support for the Tegra186 BPMP driver"
depends on TEGRA186
help
The Tegra BPMP (Boot and Power Management Processor) is a separate
auxiliary CPU embedded into Tegra to perform power management work,
and controls related features such as clocks, resets, power domains,
PMIC I2C bus, etc. This driver provides the core low-level
communication path by which feature-specific drivers (such as clock)
can make requests to the BPMP. This driver is similar to an MFD
driver in the Linux kernel.
config TEST_DRV
bool "Enable support for test drivers"
default y if SANDBOX
help
This enables drivers and uclasses that provides a way of testing the
operations of memory allocation and driver/uclass methods in driver
model. This should only be enabled for testing as it is not useful for
anything else.
config USB_HUB_USB251XB
tristate "USB251XB Hub Controller Configuration Driver"
depends on I2C
help
This option enables support for configuration via SMBus of the
Microchip USB251x/xBi USB 2.0 Hub Controller series. Configuration
parameters may be set in devicetree or platform data.
Say Y or M here if you need to configure such a device via SMBus.
config TWL4030_LED
bool "Enable TWL4030 LED controller"
help
Enable this to add support for the TWL4030 LED controller.
config WINBOND_W83627
bool "Enable Winbond Super I/O driver"
help
If you say Y here, you will get support for the Winbond
W83627 Super I/O driver. This can be used to enable the
legacy UART or other devices in the Winbond Super IO chips
on X86 platforms.
config QCOM_GENI_SE
bool "Qualcomm GENI Serial Engine Driver"
depends on ARCH_SNAPDRAGON
help
The driver manages Generic Interface (GENI) firmware based
Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
config QFW
bool
help
Hidden option to enable QEMU fw_cfg interface and uclass. This will
be selected by either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
config QFW_PIO
bool
depends on QFW
help
Hidden option to enable PIO QEMU fw_cfg interface. This will be
selected by the appropriate QEMU board.
config QFW_MMIO
bool
depends on QFW
help
Hidden option to enable MMIO QEMU fw_cfg interface. This will be
selected by the appropriate QEMU board.
config I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs"
depends on MISC
help
Enable a generic driver for EEPROMs attached via I2C.
config SPL_I2C_EEPROM
bool "Enable driver for generic I2C-attached EEPROMs for SPL"
depends on SPL_MISC
help
This option is an SPL-variant of the I2C_EEPROM option.
See the help of I2C_EEPROM for details.
config SYS_I2C_EEPROM_ADDR
hex "Chip address of the EEPROM device"
depends on ID_EEPROM || I2C_EEPROM || SPL_I2C_EEPROM || CMD_EEPROM || ENV_IS_IN_EEPROM
default 0
if I2C_EEPROM
config SYS_I2C_EEPROM_ADDR_OVERFLOW
hex "EEPROM Address Overflow"
default 0x0
help
EEPROM chips that implement "address overflow" are ones
like Catalyst 24WC04/08/16 which has 9/10/11 bits of
address and the extra bits end up in the "chip address" bit
slots. This makes a 24WC08 (1Kbyte) chip look like four 256
byte chips.
endif
config GDSYS_RXAUI_CTRL
bool "Enable gdsys RXAUI control driver"
depends on MISC
help
Support gdsys FPGA's RXAUI control.
config GDSYS_IOEP
bool "Enable gdsys IOEP driver"
depends on MISC
help
Support gdsys FPGA's IO endpoint driver.
config MPC83XX_SERDES
bool "Enable MPC83xx serdes driver"
depends on MISC
help
Support for serdes found on MPC83xx SoCs.
config FS_LOADER
bool "Enable loader driver for file system"
help
This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
config SPL_FS_LOADER
bool "Enable loader driver for file system"
depends on SPL
help
This is file system generic loader which can be used to load
the file image from the storage into target such as memory.
The consumer driver would then use this loader to program whatever,
ie. the FPGA device.
config GDSYS_SOC
bool "Enable gdsys SOC driver"
depends on MISC
help
Support for gdsys IHS SOC, a simple bus associated with each gdsys
IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
register maps are contained within the FPGA's register map.
config IHS_FPGA
bool "Enable IHS FPGA driver"
depends on MISC
help
Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
gdsys devices, which supply the majority of the functionality offered
by the devices. This driver supports both CON and CPU variants of the
devices, depending on the device tree entry.
config ESM_K3
bool "Enable K3 ESM driver"
depends on ARCH_K3
help
Support ESM (Error Signaling Module) on TI K3 SoCs.
config MICROCHIP_FLEXCOM
bool "Enable Microchip Flexcom driver"
depends on MISC
help
The Atmel Flexcom is just a wrapper which embeds a SPI controller,
an I2C controller and an USART.
Only one function can be used at a time and is chosen at boot time
according to the device tree.
config K3_AVS0
depends on ARCH_K3 && SPL_DM_REGULATOR
bool "AVS class 0 support for K3 devices"
help
K3 devices have the optimized voltage values for the main voltage
domains stored in efuse within the VTM IP. This driver reads the
optimized voltage from the efuse, so that it can be programmed
to the PMIC on board.
config ESM_PMIC
bool "Enable PMIC ESM driver"
depends on DM_PMIC
help
Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
typically to reboot the board in error condition.
config FSL_IFC
bool
config SL28CPLD
bool "Enable Kontron sl28cpld multi-function driver"
depends on DM_I2C
help
Support for the Kontron sl28cpld management controller. This is
the base driver which provides common access methods for the
sub-drivers.
endmenu