2015-08-30 16:55:38 -06:00
|
|
|
if ARCH_ROCKCHIP
|
|
|
|
|
2019-07-16 22:18:21 +02:00
|
|
|
config ROCKCHIP_PX30
|
|
|
|
bool "Support Rockchip PX30"
|
|
|
|
select ARM64
|
|
|
|
select SUPPORT_SPL
|
|
|
|
select SUPPORT_TPL
|
|
|
|
select SPL
|
|
|
|
select TPL
|
|
|
|
select TPL_TINY_FRAMEWORK if TPL
|
|
|
|
select TPL_NEEDS_SEPARATE_STACK if TPL
|
|
|
|
imply SPL_SEPARATE_BSS
|
2021-08-08 12:20:12 -06:00
|
|
|
select SPL_SERIAL
|
|
|
|
select TPL_SERIAL
|
2019-07-16 22:18:21 +02:00
|
|
|
select DEBUG_UART_BOARD_INIT
|
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
|
|
|
help
|
|
|
|
The Rockchip PX30 is a ARM-based SoC with a quad-core Cortex-A35
|
|
|
|
including NEON and GPU, Mali-400 graphics, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
|
|
|
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
|
|
|
|
|
2016-07-16 00:17:15 +02:00
|
|
|
config ROCKCHIP_RK3036
|
|
|
|
bool "Support Rockchip RK3036"
|
2018-04-26 18:21:26 +05:30
|
|
|
select CPU_V7A
|
2016-07-19 21:16:59 +08:00
|
|
|
select SUPPORT_SPL
|
|
|
|
select SPL
|
2018-01-17 09:51:41 +08:00
|
|
|
imply USB_FUNCTION_ROCKUSB
|
|
|
|
imply CMD_ROCKUSB
|
2019-07-22 20:02:04 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2016-07-16 00:17:15 +02:00
|
|
|
help
|
|
|
|
The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
|
|
|
|
including NEON and GPU, Mali-400 graphics, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
|
|
|
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
|
|
|
|
|
2017-11-28 16:04:16 +08:00
|
|
|
config ROCKCHIP_RK3128
|
|
|
|
bool "Support Rockchip RK3128"
|
2018-04-26 18:21:26 +05:30
|
|
|
select CPU_V7A
|
2019-07-22 20:02:05 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2017-11-28 16:04:16 +08:00
|
|
|
help
|
|
|
|
The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
|
|
|
|
including NEON and GPU, Mali-400 graphics, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
|
|
|
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
|
|
|
|
|
2017-02-18 19:46:36 +01:00
|
|
|
config ROCKCHIP_RK3188
|
|
|
|
bool "Support Rockchip RK3188"
|
2018-04-26 18:21:26 +05:30
|
|
|
select CPU_V7A
|
2017-05-03 17:13:32 +08:00
|
|
|
select SPL_BOARD_INIT if SPL
|
2017-02-18 19:46:36 +01:00
|
|
|
select SUPPORT_SPL
|
|
|
|
select SPL
|
2017-10-10 16:21:17 +02:00
|
|
|
select SPL_CLK
|
|
|
|
select SPL_REGMAP
|
|
|
|
select SPL_SYSCON
|
|
|
|
select SPL_RAM
|
2021-07-10 21:14:31 -06:00
|
|
|
select SPL_DRIVERS_MISC
|
2017-10-10 16:21:15 +02:00
|
|
|
select SPL_ROCKCHIP_EARLYRETURN_TO_BROM
|
2019-07-22 19:59:15 +08:00
|
|
|
select SPL_ROCKCHIP_BACK_TO_BROM
|
2017-04-06 00:19:36 +02:00
|
|
|
select BOARD_LATE_INIT
|
2019-07-22 20:02:09 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2019-07-22 19:59:18 +08:00
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
2017-02-18 19:46:36 +01:00
|
|
|
help
|
|
|
|
The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
|
|
|
|
including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
|
|
|
|
video interfaces, several memory options and video codec support.
|
|
|
|
Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S,
|
|
|
|
UART, SPI, I2C and PWMs.
|
2017-06-23 17:17:52 +08:00
|
|
|
|
|
|
|
config ROCKCHIP_RK322X
|
|
|
|
bool "Support Rockchip RK3228/RK3229"
|
2018-04-26 18:21:26 +05:30
|
|
|
select CPU_V7A
|
2017-06-23 17:17:52 +08:00
|
|
|
select SUPPORT_SPL
|
2019-04-02 20:41:24 +08:00
|
|
|
select SUPPORT_TPL
|
2017-06-23 17:17:52 +08:00
|
|
|
select SPL
|
2019-04-02 20:41:24 +08:00
|
|
|
select SPL_DM
|
|
|
|
select SPL_OF_LIBFDT
|
|
|
|
select TPL
|
|
|
|
select TPL_DM
|
|
|
|
select TPL_OF_LIBFDT
|
|
|
|
select TPL_NEEDS_SEPARATE_STACK if TPL
|
2021-07-10 21:14:31 -06:00
|
|
|
select SPL_DRIVERS_MISC
|
2019-07-22 20:02:07 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2021-08-08 12:20:12 -06:00
|
|
|
imply SPL_SERIAL
|
2019-07-22 19:59:20 +08:00
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
2021-08-08 12:20:12 -06:00
|
|
|
imply TPL_SERIAL
|
2019-07-09 22:05:56 +08:00
|
|
|
imply TPL_ROCKCHIP_COMMON_BOARD
|
2019-04-02 20:41:24 +08:00
|
|
|
select TPL_LIBCOMMON_SUPPORT
|
|
|
|
select TPL_LIBGENERIC_SUPPORT
|
2017-06-23 17:17:52 +08:00
|
|
|
help
|
|
|
|
The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
|
|
|
|
including NEON and GPU, Mali-400 graphics, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
|
|
|
USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.
|
2017-02-18 19:46:36 +01:00
|
|
|
|
2015-08-30 16:55:38 -06:00
|
|
|
config ROCKCHIP_RK3288
|
|
|
|
bool "Support Rockchip RK3288"
|
2018-04-26 18:21:26 +05:30
|
|
|
select CPU_V7A
|
2020-07-21 12:16:38 +05:30
|
|
|
select OF_BOARD_SETUP
|
2021-08-27 21:18:30 -04:00
|
|
|
select SKIP_LOWLEVEL_INIT_ONLY
|
2016-07-19 21:16:59 +08:00
|
|
|
select SUPPORT_SPL
|
|
|
|
select SPL
|
2019-07-02 11:43:05 +08:00
|
|
|
select SUPPORT_TPL
|
2020-01-23 19:42:19 +05:30
|
|
|
imply PRE_CONSOLE_BUFFER
|
2019-07-22 20:02:15 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2019-07-22 19:59:27 +08:00
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
2019-07-02 11:43:05 +08:00
|
|
|
imply TPL_CLK
|
|
|
|
imply TPL_DM
|
2021-07-10 21:14:31 -06:00
|
|
|
imply TPL_DRIVERS_MISC
|
2019-07-02 11:43:05 +08:00
|
|
|
imply TPL_LIBCOMMON_SUPPORT
|
|
|
|
imply TPL_LIBGENERIC_SUPPORT
|
2019-07-02 11:43:06 +08:00
|
|
|
imply TPL_NEEDS_SEPARATE_STACK
|
2019-07-02 11:43:05 +08:00
|
|
|
imply TPL_OF_CONTROL
|
|
|
|
imply TPL_OF_PLATDATA
|
|
|
|
imply TPL_RAM
|
|
|
|
imply TPL_REGMAP
|
2019-07-09 22:05:57 +08:00
|
|
|
imply TPL_ROCKCHIP_COMMON_BOARD
|
2021-08-08 12:20:12 -06:00
|
|
|
imply TPL_SERIAL
|
2019-07-02 11:43:05 +08:00
|
|
|
imply TPL_SYSCON
|
2017-12-15 08:17:13 +08:00
|
|
|
imply USB_FUNCTION_ROCKUSB
|
|
|
|
imply CMD_ROCKUSB
|
2015-08-30 16:55:38 -06:00
|
|
|
help
|
|
|
|
The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
|
|
|
|
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
|
|
|
|
video interfaces supporting HDMI and eDP, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
2016-11-02 18:03:01 +01:00
|
|
|
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
2015-08-30 16:55:38 -06:00
|
|
|
|
2019-11-14 11:21:12 +08:00
|
|
|
config ROCKCHIP_RK3308
|
|
|
|
bool "Support Rockchip RK3308"
|
|
|
|
select ARM64
|
|
|
|
select DEBUG_UART_BOARD_INIT
|
|
|
|
select SUPPORT_SPL
|
|
|
|
select SUPPORT_TPL
|
|
|
|
select SPL
|
|
|
|
select SPL_ATF
|
|
|
|
select SPL_ATF_NO_PLATFORM_PARAM
|
|
|
|
select SPL_LOAD_FIT
|
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
|
|
|
imply SPL_CLK
|
|
|
|
imply SPL_REGMAP
|
|
|
|
imply SPL_SYSCON
|
|
|
|
imply SPL_RAM
|
2021-08-08 12:20:12 -06:00
|
|
|
imply SPL_SERIAL
|
|
|
|
imply TPL_SERIAL
|
2019-11-14 11:21:12 +08:00
|
|
|
imply SPL_SEPARATE_BSS
|
|
|
|
help
|
|
|
|
The Rockchip RK3308 is a ARM-based Soc which embedded with quad
|
|
|
|
Cortex-A35 and highly integrated audio interfaces.
|
|
|
|
|
2017-02-23 15:37:51 +08:00
|
|
|
config ROCKCHIP_RK3328
|
|
|
|
bool "Support Rockchip RK3328"
|
|
|
|
select ARM64
|
2019-06-09 00:27:15 +03:00
|
|
|
select SUPPORT_SPL
|
|
|
|
select SPL
|
2019-08-02 10:40:01 +03:00
|
|
|
select SUPPORT_TPL
|
|
|
|
select TPL
|
|
|
|
select TPL_NEEDS_SEPARATE_STACK if TPL
|
2019-07-22 20:02:16 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2019-11-15 11:04:44 +08:00
|
|
|
imply ROCKCHIP_SDRAM_COMMON
|
2019-07-22 19:59:32 +08:00
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
2021-08-08 12:20:12 -06:00
|
|
|
imply SPL_SERIAL
|
|
|
|
imply TPL_SERIAL
|
2019-06-09 00:27:15 +03:00
|
|
|
imply SPL_SEPARATE_BSS
|
|
|
|
select ENABLE_ARM_SOC_BOOT0_HOOK
|
|
|
|
select DEBUG_UART_BOARD_INIT
|
|
|
|
select SYS_NS16550
|
2017-02-23 15:37:51 +08:00
|
|
|
help
|
|
|
|
The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53.
|
|
|
|
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
|
|
|
|
video interfaces supporting HDMI and eDP, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
|
|
|
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
|
|
|
|
2017-05-15 17:51:18 +08:00
|
|
|
config ROCKCHIP_RK3368
|
|
|
|
bool "Support Rockchip RK3368"
|
|
|
|
select ARM64
|
2017-06-11 23:46:25 +02:00
|
|
|
select SUPPORT_SPL
|
|
|
|
select SUPPORT_TPL
|
2017-07-28 20:03:07 +02:00
|
|
|
select TPL_NEEDS_SEPARATE_STACK if TPL
|
2019-07-22 20:02:17 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2019-07-22 19:59:34 +08:00
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
2017-06-11 23:46:25 +02:00
|
|
|
imply SPL_SEPARATE_BSS
|
2021-08-08 12:20:12 -06:00
|
|
|
imply SPL_SERIAL
|
|
|
|
imply TPL_SERIAL
|
2019-07-09 22:05:58 +08:00
|
|
|
imply TPL_ROCKCHIP_COMMON_BOARD
|
2017-05-15 17:51:18 +08:00
|
|
|
help
|
2017-06-10 00:47:53 +02:00
|
|
|
The Rockchip RK3368 is a ARM-based SoC with a octa-core (organised
|
|
|
|
into a big and little cluster with 4 cores each) Cortex-A53 including
|
|
|
|
AdvSIMD, 512KB L2 cache (for the big cluster) and 256 KB L2 cache
|
|
|
|
(for the little cluster), PowerVR G6110 based graphics, one video
|
|
|
|
output processor supporting LVDS/HDMI/eDP, several DDR3 options and
|
|
|
|
video codec support.
|
|
|
|
|
|
|
|
On-chip peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO,
|
|
|
|
I2S, UARTs, SPI, I2C and PWMs.
|
2017-05-15 17:51:18 +08:00
|
|
|
|
2016-07-19 21:16:59 +08:00
|
|
|
config ROCKCHIP_RK3399
|
|
|
|
bool "Support Rockchip RK3399"
|
|
|
|
select ARM64
|
2017-02-22 16:56:38 +08:00
|
|
|
select SUPPORT_SPL
|
2018-11-09 11:18:15 +08:00
|
|
|
select SUPPORT_TPL
|
2017-02-22 16:56:38 +08:00
|
|
|
select SPL
|
2019-05-08 11:11:43 +05:30
|
|
|
select SPL_ATF
|
2019-06-21 00:25:03 +05:30
|
|
|
select SPL_BOARD_INIT if SPL
|
2019-05-08 11:11:43 +05:30
|
|
|
select SPL_LOAD_FIT
|
|
|
|
select SPL_CLK if SPL
|
|
|
|
select SPL_PINCTRL if SPL
|
|
|
|
select SPL_RAM if SPL
|
|
|
|
select SPL_REGMAP if SPL
|
|
|
|
select SPL_SYSCON if SPL
|
2018-11-09 11:18:15 +08:00
|
|
|
select TPL_NEEDS_SEPARATE_STACK if TPL
|
2017-02-22 16:56:38 +08:00
|
|
|
select SPL_SEPARATE_BSS
|
2021-08-08 12:20:12 -06:00
|
|
|
select SPL_SERIAL
|
2021-07-10 21:14:31 -06:00
|
|
|
select SPL_DRIVERS_MISC
|
2019-05-08 11:11:43 +05:30
|
|
|
select CLK
|
|
|
|
select FIT
|
|
|
|
select PINCTRL
|
|
|
|
select RAM
|
|
|
|
select REGMAP
|
|
|
|
select SYSCON
|
|
|
|
select DM_PMIC
|
|
|
|
select DM_REGULATOR_FIXED
|
2017-10-11 15:00:16 +08:00
|
|
|
select BOARD_LATE_INIT
|
2020-04-02 17:11:23 +05:30
|
|
|
imply PRE_CONSOLE_BUFFER
|
2019-07-22 20:02:19 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2019-11-15 11:04:45 +08:00
|
|
|
imply ROCKCHIP_SDRAM_COMMON
|
2020-06-16 00:30:47 +01:00
|
|
|
imply SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF
|
2019-07-22 19:59:42 +08:00
|
|
|
imply SPL_ROCKCHIP_COMMON_BOARD
|
2021-08-08 12:20:12 -06:00
|
|
|
imply TPL_SERIAL
|
2018-11-09 11:18:15 +08:00
|
|
|
imply TPL_LIBCOMMON_SUPPORT
|
|
|
|
imply TPL_LIBGENERIC_SUPPORT
|
|
|
|
imply TPL_SYS_MALLOC_SIMPLE
|
2021-07-10 21:14:31 -06:00
|
|
|
imply TPL_DRIVERS_MISC
|
2018-11-09 11:18:15 +08:00
|
|
|
imply TPL_OF_CONTROL
|
|
|
|
imply TPL_DM
|
|
|
|
imply TPL_REGMAP
|
|
|
|
imply TPL_SYSCON
|
|
|
|
imply TPL_RAM
|
|
|
|
imply TPL_CLK
|
|
|
|
imply TPL_TINY_MEMSET
|
2019-07-09 22:06:01 +08:00
|
|
|
imply TPL_ROCKCHIP_COMMON_BOARD
|
2020-01-09 14:22:19 +05:30
|
|
|
imply SYS_BOOTCOUNT_SINGLEWORD if BOOTCOUNT_LIMIT
|
|
|
|
imply CMD_BOOTCOUNT if BOOTCOUNT_LIMIT
|
2016-07-19 21:16:59 +08:00
|
|
|
help
|
|
|
|
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
|
|
|
|
and quad-core Cortex-A53.
|
|
|
|
including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
|
|
|
|
video interfaces supporting HDMI and eDP, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
|
|
|
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
|
|
|
|
2021-06-02 15:58:25 +08:00
|
|
|
config ROCKCHIP_RK3568
|
|
|
|
bool "Support Rockchip RK3568"
|
|
|
|
select ARM64
|
2021-10-26 10:42:19 +08:00
|
|
|
select SUPPORT_SPL
|
|
|
|
select SPL
|
2021-06-02 15:58:25 +08:00
|
|
|
select CLK
|
|
|
|
select PINCTRL
|
|
|
|
select RAM
|
|
|
|
select REGMAP
|
|
|
|
select SYSCON
|
|
|
|
select BOARD_LATE_INIT
|
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
|
|
|
help
|
|
|
|
The Rockchip RK3568 is a ARM-based SoC with quad-core Cortex-A55,
|
|
|
|
including NEON and GPU, 512K L3 cache, Mali-G52 based graphics,
|
|
|
|
two video interfaces supporting HDMI and eDP, several DDR3 options
|
|
|
|
and video codec support. Peripherals include Gigabit Ethernet,
|
|
|
|
USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs.
|
|
|
|
|
2017-06-01 18:00:55 +08:00
|
|
|
config ROCKCHIP_RV1108
|
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|
|
bool "Support Rockchip RV1108"
|
2018-04-26 18:21:26 +05:30
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|
|
select CPU_V7A
|
2019-07-22 20:02:21 +08:00
|
|
|
imply ROCKCHIP_COMMON_BOARD
|
2017-06-01 18:00:55 +08:00
|
|
|
help
|
|
|
|
The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
|
|
|
|
and a DSP.
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|
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|
2018-10-08 13:01:56 +02:00
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|
|
config ROCKCHIP_USB_UART
|
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|
|
bool "Route uart output to usb pins"
|
|
|
|
help
|
|
|
|
Rockchip SoCs have the ability to route the signals of the debug
|
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|
|
uart through the d+ and d- pins of a specific usb phy to enable
|
|
|
|
some form of closed-case debugging. With this option supported
|
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|
|
SoCs will enable this routing as a debug measure.
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|
|
2017-06-29 11:21:15 +02:00
|
|
|
config SPL_ROCKCHIP_BACK_TO_BROM
|
2016-07-12 19:09:49 +08:00
|
|
|
bool "SPL returns to bootrom"
|
|
|
|
default y if ROCKCHIP_RK3036
|
2017-02-18 19:46:25 +01:00
|
|
|
select ROCKCHIP_BROM_HELPER
|
2019-07-22 19:59:15 +08:00
|
|
|
select SPL_BOOTROM_SUPPORT
|
2017-06-29 11:21:15 +02:00
|
|
|
depends on SPL
|
|
|
|
help
|
|
|
|
Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
|
|
|
|
SPL will return to the boot rom, which will then load the U-Boot
|
|
|
|
binary to keep going on.
|
|
|
|
|
|
|
|
config TPL_ROCKCHIP_BACK_TO_BROM
|
|
|
|
bool "TPL returns to bootrom"
|
2018-11-09 11:18:15 +08:00
|
|
|
default y
|
2017-06-29 11:21:15 +02:00
|
|
|
select ROCKCHIP_BROM_HELPER
|
2019-07-22 19:59:15 +08:00
|
|
|
select TPL_BOOTROM_SUPPORT
|
2017-06-29 11:21:15 +02:00
|
|
|
depends on TPL
|
2016-07-12 19:09:49 +08:00
|
|
|
help
|
|
|
|
Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled,
|
|
|
|
SPL will return to the boot rom, which will then load the U-Boot
|
|
|
|
binary to keep going on.
|
|
|
|
|
2019-07-22 20:02:01 +08:00
|
|
|
config ROCKCHIP_COMMON_BOARD
|
|
|
|
bool "Rockchip common board file"
|
|
|
|
help
|
|
|
|
Rockchip SoCs have similar boot process, Common board file is mainly
|
|
|
|
in charge of common process of board_init() and board_late_init() for
|
|
|
|
U-Boot proper.
|
|
|
|
|
2019-07-22 19:59:12 +08:00
|
|
|
config SPL_ROCKCHIP_COMMON_BOARD
|
|
|
|
bool "Rockchip SPL common board file"
|
|
|
|
depends on SPL
|
|
|
|
help
|
|
|
|
Rockchip SoCs have similar boot process, SPL is mainly in charge of
|
|
|
|
load and boot Trust ATF/U-Boot firmware, and DRAM init if there is
|
|
|
|
no TPL for the board.
|
|
|
|
|
2019-07-09 22:05:55 +08:00
|
|
|
config TPL_ROCKCHIP_COMMON_BOARD
|
2019-12-20 18:05:22 -08:00
|
|
|
bool "Rockchip TPL common board file"
|
2019-07-09 22:05:55 +08:00
|
|
|
depends on TPL
|
|
|
|
help
|
|
|
|
Rockchip SoCs have similar boot process, prefer to use TPL for DRAM
|
|
|
|
init and back to bootrom, and SPL as Trust ATF/U-Boot loader. TPL
|
|
|
|
common board is a basic TPL board init which can be shared for most
|
2019-11-13 18:18:03 -08:00
|
|
|
of SoCs to avoid copy-paste for different SoCs.
|
2019-07-09 22:05:55 +08:00
|
|
|
|
2017-10-11 15:00:16 +08:00
|
|
|
config ROCKCHIP_BOOT_MODE_REG
|
|
|
|
hex "Rockchip boot mode flag register address"
|
|
|
|
help
|
2019-03-28 11:01:23 +08:00
|
|
|
The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h)
|
2017-10-11 15:00:16 +08:00
|
|
|
according to the value from this register.
|
|
|
|
|
2017-04-20 17:03:46 +08:00
|
|
|
config ROCKCHIP_SPL_RESERVE_IRAM
|
|
|
|
hex "Size of IRAM reserved in SPL"
|
2017-12-18 15:13:19 +08:00
|
|
|
default 0
|
2017-04-20 17:03:46 +08:00
|
|
|
help
|
|
|
|
SPL may need reserve memory for firmware loaded by SPL, whose load
|
|
|
|
address is in IRAM and may overlay with SPL text area if not
|
|
|
|
reserved.
|
|
|
|
|
2017-02-18 19:46:25 +01:00
|
|
|
config ROCKCHIP_BROM_HELPER
|
|
|
|
bool
|
|
|
|
|
2017-10-10 16:21:10 +02:00
|
|
|
config SPL_ROCKCHIP_EARLYRETURN_TO_BROM
|
|
|
|
bool "SPL requires early-return (for RK3188-style BROM) to BROM"
|
|
|
|
depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK
|
|
|
|
help
|
|
|
|
Some Rockchip BROM variants (e.g. on the RK3188) load the
|
|
|
|
first stage in segments and enter multiple times. E.g. on
|
|
|
|
the RK3188, the first 1KB of the first stage are loaded
|
|
|
|
first and entered; after returning to the BROM, the
|
|
|
|
remainder of the first stage is loaded, but the BROM
|
|
|
|
re-enters at the same address/to the same code as previously.
|
|
|
|
|
|
|
|
This enables support code in the BOOT0 hook for the SPL stage
|
|
|
|
to allow multiple entries.
|
|
|
|
|
|
|
|
config TPL_ROCKCHIP_EARLYRETURN_TO_BROM
|
|
|
|
bool "TPL requires early-return (for RK3188-style BROM) to BROM"
|
|
|
|
depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK
|
|
|
|
help
|
|
|
|
Some Rockchip BROM variants (e.g. on the RK3188) load the
|
|
|
|
first stage in segments and enter multiple times. E.g. on
|
|
|
|
the RK3188, the first 1KB of the first stage are loaded
|
|
|
|
first and entered; after returning to the BROM, the
|
|
|
|
remainder of the first stage is loaded, but the BROM
|
|
|
|
re-enters at the same address/to the same code as previously.
|
|
|
|
|
|
|
|
This enables support code in the BOOT0 hook for the TPL stage
|
|
|
|
to allow multiple entries.
|
|
|
|
|
2021-08-08 12:20:09 -06:00
|
|
|
config SPL_MMC
|
2017-06-29 11:21:15 +02:00
|
|
|
default y if !SPL_ROCKCHIP_BACK_TO_BROM
|
2016-08-29 07:31:16 -04:00
|
|
|
|
2020-07-19 13:55:57 -06:00
|
|
|
config ROCKCHIP_SPI_IMAGE
|
|
|
|
bool "Build a SPI image for rockchip"
|
|
|
|
depends on HAS_ROM
|
|
|
|
help
|
|
|
|
Some Rockchip SoCs support booting from SPI flash. Enable this
|
|
|
|
option to produce a 4MB SPI-flash image (called u-boot.rom)
|
|
|
|
containing U-Boot. The image is built by binman. U-Boot sits near
|
|
|
|
the start of the image.
|
|
|
|
|
2019-07-16 22:18:21 +02:00
|
|
|
source "arch/arm/mach-rockchip/px30/Kconfig"
|
2015-11-17 14:20:27 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk3036/Kconfig"
|
2017-11-28 16:04:16 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk3128/Kconfig"
|
2017-02-18 19:46:36 +01:00
|
|
|
source "arch/arm/mach-rockchip/rk3188/Kconfig"
|
2017-06-23 17:17:54 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk322x/Kconfig"
|
2016-07-16 00:17:15 +02:00
|
|
|
source "arch/arm/mach-rockchip/rk3288/Kconfig"
|
2019-11-14 11:21:12 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk3308/Kconfig"
|
2017-02-23 15:37:51 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk3328/Kconfig"
|
2017-05-15 17:51:18 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk3368/Kconfig"
|
2016-07-19 21:16:59 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk3399/Kconfig"
|
2021-06-02 16:13:46 +08:00
|
|
|
source "arch/arm/mach-rockchip/rk3568/Kconfig"
|
2017-06-01 18:00:55 +08:00
|
|
|
source "arch/arm/mach-rockchip/rv1108/Kconfig"
|
2015-08-30 16:55:38 -06:00
|
|
|
endif
|