2014-07-30 05:08:14 +00:00
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menu "x86 architecture"
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depends on X86
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config SYS_ARCH
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default "x86"
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2017-01-16 14:03:43 +00:00
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choice
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prompt "Run U-Boot in 32/64-bit mode"
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default X86_RUN_32BIT
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help
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U-Boot can be built as a 32-bit binary which runs in 32-bit mode
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even on 64-bit machines. In this case SPL is not used, and U-Boot
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runs directly from the reset vector (via 16-bit start-up).
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Alternatively it can be run as a 64-bit binary, thus requiring a
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64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit
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start-up) then jumps to U-Boot in 64-bit mode.
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For now, 32-bit mode is recommended, as 64-bit is still
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experimental and is missing a lot of features.
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config X86_RUN_32BIT
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bool "32-bit"
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help
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Build U-Boot as a 32-bit binary with no SPL. This is the currently
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supported normal setup. U-Boot will stay in 32-bit mode even on
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64-bit machines. When booting a 64-bit kernel, U-Boot will switch
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to 64-bit just before starting the kernel. Only the bottom 4GB of
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memory can be accessed through normal means, although
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arch_phys_memset() can be used for basic access to other memory.
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config X86_RUN_64BIT
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bool "64-bit"
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select X86_64
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select SPL
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select SPL_SEPARATE_BSS
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help
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Build U-Boot as a 64-bit binary with a 32-bit SPL. This is
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experimental and many features are missing. U-Boot SPL starts up,
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runs through the 16-bit and 32-bit init, then switches to 64-bit
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mode and jumps to U-Boot proper.
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endchoice
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config X86_64
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bool
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config SPL_X86_64
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bool
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depends on SPL
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2014-07-30 05:08:14 +00:00
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choice
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2015-04-27 15:22:24 +00:00
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prompt "Mainboard vendor"
|
2015-05-07 13:34:09 +00:00
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default VENDOR_EMULATION
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2014-07-30 05:08:14 +00:00
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2016-06-21 17:07:33 +00:00
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config VENDOR_ADVANTECH
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bool "advantech"
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2016-03-16 07:48:21 +00:00
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config VENDOR_CONGATEC
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bool "congatec"
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2015-04-27 15:22:24 +00:00
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config VENDOR_COREBOOT
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bool "coreboot"
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2015-01-28 05:13:47 +00:00
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2016-08-15 11:50:49 +00:00
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config VENDOR_DFI
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bool "dfi"
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2015-08-04 18:33:46 +00:00
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config VENDOR_EFI
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bool "efi"
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2015-05-07 13:34:08 +00:00
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config VENDOR_EMULATION
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bool "emulation"
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2015-04-27 15:22:24 +00:00
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config VENDOR_GOOGLE
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bool "Google"
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2015-01-28 05:13:47 +00:00
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2015-04-27 15:22:24 +00:00
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config VENDOR_INTEL
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bool "Intel"
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2015-02-02 14:35:29 +00:00
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2014-07-30 05:08:14 +00:00
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endchoice
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2017-02-17 13:48:58 +00:00
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# subarchitectures-specific options below
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config INTEL_MID
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bool "Intel MID platform support"
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2017-04-01 13:21:33 +00:00
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select REGMAP
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select SYSCON
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2017-02-17 13:48:58 +00:00
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help
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Select to build a U-Boot capable of supporting Intel MID
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(Mobile Internet Device) platform systems which do not have
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the PCI legacy interfaces.
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If you are building for a PC class system say N here.
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Intel MID platforms are based on an Intel processor and
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chipset which consume less power than most of the x86
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derivatives.
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2015-04-27 15:22:24 +00:00
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# board-specific options below
|
2016-06-21 17:07:33 +00:00
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source "board/advantech/Kconfig"
|
2016-03-16 07:48:21 +00:00
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source "board/congatec/Kconfig"
|
2015-04-27 15:22:24 +00:00
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source "board/coreboot/Kconfig"
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2016-08-15 11:50:49 +00:00
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source "board/dfi/Kconfig"
|
2015-08-04 18:33:47 +00:00
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source "board/efi/Kconfig"
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2015-05-07 13:34:08 +00:00
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source "board/emulation/Kconfig"
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2015-04-27 15:22:24 +00:00
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source "board/google/Kconfig"
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source "board/intel/Kconfig"
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2015-04-27 15:22:25 +00:00
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# platform-specific options below
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source "arch/x86/cpu/baytrail/Kconfig"
|
2017-08-16 05:41:58 +00:00
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source "arch/x86/cpu/braswell/Kconfig"
|
2016-03-12 05:07:18 +00:00
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source "arch/x86/cpu/broadwell/Kconfig"
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2015-04-27 15:22:25 +00:00
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source "arch/x86/cpu/coreboot/Kconfig"
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source "arch/x86/cpu/ivybridge/Kconfig"
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2018-06-12 15:36:16 +00:00
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source "arch/x86/cpu/efi/Kconfig"
|
2015-05-07 13:34:08 +00:00
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source "arch/x86/cpu/qemu/Kconfig"
|
2015-04-27 15:22:25 +00:00
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source "arch/x86/cpu/quark/Kconfig"
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source "arch/x86/cpu/queensbay/Kconfig"
|
2017-07-06 11:41:52 +00:00
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source "arch/x86/cpu/tangier/Kconfig"
|
2015-04-27 15:22:25 +00:00
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# architecture-specific options below
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2016-05-01 17:35:52 +00:00
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config AHCI
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default y
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2015-02-11 23:32:59 +00:00
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config SYS_MALLOC_F_LEN
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default 0x800
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2014-11-13 05:42:10 +00:00
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config RAMBASE
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hex
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default 0x100000
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config XIP_ROM_SIZE
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hex
|
2015-01-06 14:14:16 +00:00
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depends on X86_RESET_VECTOR
|
2015-01-01 23:17:54 +00:00
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default ROM_SIZE
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2014-11-13 05:42:10 +00:00
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config CPU_ADDR_BITS
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int
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default 36
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2014-11-13 05:42:28 +00:00
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config HPET_ADDRESS
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hex
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default 0xfed00000 if !HPET_ADDRESS_OVERRIDE
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config SMM_TSEG
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bool
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default n
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config SMM_TSEG_SIZE
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hex
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|
2015-01-06 14:14:15 +00:00
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config X86_RESET_VECTOR
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bool
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default n
|
2017-10-17 04:42:44 +00:00
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select BINMAN
|
2015-01-06 14:14:15 +00:00
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|
2017-01-16 14:03:44 +00:00
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# The following options control where the 16-bit and 32-bit init lies
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# If SPL is enabled then it normally holds this init code, and U-Boot proper
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# is normally a 64-bit build.
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#
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# The 16-bit init refers to the reset vector and the small amount of code to
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# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper,
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# or missing altogether if U-Boot is started from EFI or coreboot.
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#
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# The 32-bit init refers to processor init, running binary blobs including
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# FSP, setting up interrupts and anything else that needs to be done in
|
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# 32-bit code. It is normally in the same place as 16-bit init if that is
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# enabled (i.e. they are both in SPL, or both in U-Boot proper).
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config X86_16BIT_INIT
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bool
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depends on X86_RESET_VECTOR
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default y if X86_RESET_VECTOR && !SPL
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help
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|
This is enabled when 16-bit init is in U-Boot proper
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config SPL_X86_16BIT_INIT
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bool
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depends on X86_RESET_VECTOR
|
2019-04-26 03:58:46 +00:00
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default y if X86_RESET_VECTOR && SPL && !TPL
|
2017-01-16 14:03:44 +00:00
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|
|
help
|
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|
|
This is enabled when 16-bit init is in SPL
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|
|
2019-04-26 03:58:46 +00:00
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config TPL_X86_16BIT_INIT
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bool
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depends on X86_RESET_VECTOR
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default y if X86_RESET_VECTOR && TPL
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help
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|
This is enabled when 16-bit init is in TPL
|
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|
|
2017-01-16 14:03:44 +00:00
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|
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config X86_32BIT_INIT
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bool
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depends on X86_RESET_VECTOR
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default y if X86_RESET_VECTOR && !SPL
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help
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|
This is enabled when 32-bit init is in U-Boot proper
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config SPL_X86_32BIT_INIT
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bool
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depends on X86_RESET_VECTOR
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default y if X86_RESET_VECTOR && SPL
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help
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|
|
This is enabled when 32-bit init is in SPL
|
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|
|
2015-06-07 03:33:12 +00:00
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config RESET_SEG_START
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hex
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depends on X86_RESET_VECTOR
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default 0xffff0000
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config RESET_SEG_SIZE
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hex
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depends on X86_RESET_VECTOR
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default 0x10000
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config RESET_VEC_LOC
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hex
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depends on X86_RESET_VECTOR
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default 0xfffffff0
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|
2015-01-06 14:14:15 +00:00
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|
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config SYS_X86_START16
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hex
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depends on X86_RESET_VECTOR
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default 0xfffff800
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|
2017-02-05 13:52:00 +00:00
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|
|
config X86_LOAD_FROM_32_BIT
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|
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bool "Boot from a 32-bit program"
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help
|
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|
|
Define this to boot U-Boot from a 32-bit program which sets
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the GDT differently. This can be used to boot directly from
|
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any stage of coreboot, for example, bypassing the normal
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|
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payload-loading feature.
|
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|
|
2014-12-12 13:05:19 +00:00
|
|
|
config BOARD_ROMSIZE_KB_512
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bool
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|
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config BOARD_ROMSIZE_KB_1024
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|
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bool
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|
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config BOARD_ROMSIZE_KB_2048
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bool
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|
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config BOARD_ROMSIZE_KB_4096
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bool
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|
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config BOARD_ROMSIZE_KB_8192
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bool
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|
|
config BOARD_ROMSIZE_KB_16384
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bool
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|
choice
|
|
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|
|
prompt "ROM chip size"
|
2015-01-06 14:14:16 +00:00
|
|
|
depends on X86_RESET_VECTOR
|
2014-12-12 13:05:19 +00:00
|
|
|
default UBOOT_ROMSIZE_KB_512 if BOARD_ROMSIZE_KB_512
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default UBOOT_ROMSIZE_KB_1024 if BOARD_ROMSIZE_KB_1024
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default UBOOT_ROMSIZE_KB_2048 if BOARD_ROMSIZE_KB_2048
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|
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default UBOOT_ROMSIZE_KB_4096 if BOARD_ROMSIZE_KB_4096
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|
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default UBOOT_ROMSIZE_KB_8192 if BOARD_ROMSIZE_KB_8192
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|
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|
|
default UBOOT_ROMSIZE_KB_16384 if BOARD_ROMSIZE_KB_16384
|
|
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|
|
help
|
|
|
|
|
Select the size of the ROM chip you intend to flash U-Boot on.
|
|
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|
|
The build system will take care of creating a u-boot.rom file
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|
|
|
of the matching size.
|
|
|
|
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|
|
config UBOOT_ROMSIZE_KB_512
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|
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|
|
bool "512 KB"
|
|
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|
|
help
|
|
|
|
|
Choose this option if you have a 512 KB ROM chip.
|
|
|
|
|
|
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|
|
config UBOOT_ROMSIZE_KB_1024
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|
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|
|
bool "1024 KB (1 MB)"
|
|
|
|
|
help
|
|
|
|
|
Choose this option if you have a 1024 KB (1 MB) ROM chip.
|
|
|
|
|
|
|
|
|
|
config UBOOT_ROMSIZE_KB_2048
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|
|
|
|
bool "2048 KB (2 MB)"
|
|
|
|
|
help
|
|
|
|
|
Choose this option if you have a 2048 KB (2 MB) ROM chip.
|
|
|
|
|
|
|
|
|
|
config UBOOT_ROMSIZE_KB_4096
|
|
|
|
|
bool "4096 KB (4 MB)"
|
|
|
|
|
help
|
|
|
|
|
Choose this option if you have a 4096 KB (4 MB) ROM chip.
|
|
|
|
|
|
|
|
|
|
config UBOOT_ROMSIZE_KB_8192
|
|
|
|
|
bool "8192 KB (8 MB)"
|
|
|
|
|
help
|
|
|
|
|
Choose this option if you have a 8192 KB (8 MB) ROM chip.
|
|
|
|
|
|
|
|
|
|
config UBOOT_ROMSIZE_KB_16384
|
|
|
|
|
bool "16384 KB (16 MB)"
|
|
|
|
|
help
|
|
|
|
|
Choose this option if you have a 16384 KB (16 MB) ROM chip.
|
|
|
|
|
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|
|
endchoice
|
|
|
|
|
|
|
|
|
|
# Map the config names to an integer (KB).
|
|
|
|
|
config UBOOT_ROMSIZE_KB
|
|
|
|
|
int
|
|
|
|
|
default 512 if UBOOT_ROMSIZE_KB_512
|
|
|
|
|
default 1024 if UBOOT_ROMSIZE_KB_1024
|
|
|
|
|
default 2048 if UBOOT_ROMSIZE_KB_2048
|
|
|
|
|
default 4096 if UBOOT_ROMSIZE_KB_4096
|
|
|
|
|
default 8192 if UBOOT_ROMSIZE_KB_8192
|
|
|
|
|
default 16384 if UBOOT_ROMSIZE_KB_16384
|
|
|
|
|
|
|
|
|
|
# Map the config names to a hex value (bytes).
|
2014-11-13 05:42:08 +00:00
|
|
|
config ROM_SIZE
|
|
|
|
|
hex
|
2014-12-12 13:05:19 +00:00
|
|
|
default 0x80000 if UBOOT_ROMSIZE_KB_512
|
|
|
|
|
default 0x100000 if UBOOT_ROMSIZE_KB_1024
|
|
|
|
|
default 0x200000 if UBOOT_ROMSIZE_KB_2048
|
|
|
|
|
default 0x400000 if UBOOT_ROMSIZE_KB_4096
|
|
|
|
|
default 0x800000 if UBOOT_ROMSIZE_KB_8192
|
|
|
|
|
default 0xc00000 if UBOOT_ROMSIZE_KB_12288
|
|
|
|
|
default 0x1000000 if UBOOT_ROMSIZE_KB_16384
|
2014-11-13 05:42:08 +00:00
|
|
|
|
|
|
|
|
config HAVE_INTEL_ME
|
|
|
|
|
bool "Platform requires Intel Management Engine"
|
|
|
|
|
help
|
|
|
|
|
Newer higher-end devices have an Intel Management Engine (ME)
|
|
|
|
|
which is a very large binary blob (typically 1.5MB) which is
|
|
|
|
|
required for the platform to work. This enforces a particular
|
|
|
|
|
SPI flash format. You will need to supply the me.bin file in
|
|
|
|
|
your board directory.
|
|
|
|
|
|
2014-11-13 05:42:28 +00:00
|
|
|
config X86_RAMTEST
|
|
|
|
|
bool "Perform a simple RAM test after SDRAM initialisation"
|
|
|
|
|
help
|
|
|
|
|
If there is something wrong with SDRAM then the platform will
|
|
|
|
|
often crash within U-Boot or the kernel. This option enables a
|
|
|
|
|
very simple RAM test that quickly checks whether the SDRAM seems
|
|
|
|
|
to work correctly. It is not exhaustive but can save time by
|
|
|
|
|
detecting obvious failures.
|
|
|
|
|
|
2017-03-30 10:58:10 +00:00
|
|
|
config FLASH_DESCRIPTOR_FILE
|
|
|
|
|
string "Flash descriptor binary filename"
|
|
|
|
|
depends on HAVE_INTEL_ME
|
|
|
|
|
default "descriptor.bin"
|
|
|
|
|
help
|
|
|
|
|
The filename of the file to use as flash descriptor in the
|
|
|
|
|
board directory.
|
|
|
|
|
|
|
|
|
|
config INTEL_ME_FILE
|
|
|
|
|
string "Intel Management Engine binary filename"
|
|
|
|
|
depends on HAVE_INTEL_ME
|
|
|
|
|
default "me.bin"
|
|
|
|
|
help
|
|
|
|
|
The filename of the file to use as Intel Management Engine in the
|
|
|
|
|
board directory.
|
|
|
|
|
|
2015-01-28 05:13:41 +00:00
|
|
|
config HAVE_FSP
|
|
|
|
|
bool "Add an Firmware Support Package binary"
|
2015-08-04 18:34:00 +00:00
|
|
|
depends on !EFI
|
2015-01-28 05:13:41 +00:00
|
|
|
help
|
|
|
|
|
Select this option to add an Firmware Support Package binary to
|
|
|
|
|
the resulting U-Boot image. It is a binary blob which U-Boot uses
|
|
|
|
|
to set up SDRAM and other chipset specific initialization.
|
|
|
|
|
|
|
|
|
|
Note: Without this binary U-Boot will not be able to set up its
|
|
|
|
|
SDRAM so will not boot.
|
|
|
|
|
|
|
|
|
|
config FSP_FILE
|
|
|
|
|
string "Firmware Support Package binary filename"
|
|
|
|
|
depends on HAVE_FSP
|
|
|
|
|
default "fsp.bin"
|
|
|
|
|
help
|
|
|
|
|
The filename of the file to use as Firmware Support Package binary
|
|
|
|
|
in the board directory.
|
|
|
|
|
|
|
|
|
|
config FSP_ADDR
|
|
|
|
|
hex "Firmware Support Package binary location"
|
|
|
|
|
depends on HAVE_FSP
|
|
|
|
|
default 0xfffc0000
|
|
|
|
|
help
|
|
|
|
|
FSP is not Position Independent Code (PIC) and the whole FSP has to
|
|
|
|
|
be rebased if it is placed at a location which is different from the
|
|
|
|
|
perferred base address specified during the FSP build. Use Intel's
|
|
|
|
|
Binary Configuration Tool (BCT) to do the rebase.
|
|
|
|
|
|
|
|
|
|
The default base address of 0xfffc0000 indicates that the binary must
|
|
|
|
|
be located at offset 0xc0000 from the beginning of a 1MB flash device.
|
|
|
|
|
|
|
|
|
|
config FSP_TEMP_RAM_ADDR
|
|
|
|
|
hex
|
2015-06-01 13:07:23 +00:00
|
|
|
depends on HAVE_FSP
|
2015-01-28 05:13:41 +00:00
|
|
|
default 0x2000000
|
|
|
|
|
help
|
2015-08-20 13:40:20 +00:00
|
|
|
Stack top address which is used in fsp_init() after DRAM is ready and
|
2015-01-28 05:13:41 +00:00
|
|
|
CAR is disabled.
|
|
|
|
|
|
2015-08-20 13:40:19 +00:00
|
|
|
config FSP_SYS_MALLOC_F_LEN
|
|
|
|
|
hex
|
|
|
|
|
depends on HAVE_FSP
|
|
|
|
|
default 0x100000
|
|
|
|
|
help
|
|
|
|
|
Additional size of malloc() pool before relocation.
|
|
|
|
|
|
2015-12-11 06:03:01 +00:00
|
|
|
config FSP_USE_UPD
|
|
|
|
|
bool
|
|
|
|
|
depends on HAVE_FSP
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Most FSPs use UPD data region for some FSP customization. But there
|
|
|
|
|
are still some FSPs that might not even have UPD. For such FSPs,
|
|
|
|
|
override this to n in their platform Kconfig files.
|
|
|
|
|
|
2016-02-17 08:16:23 +00:00
|
|
|
config FSP_BROKEN_HOB
|
|
|
|
|
bool
|
|
|
|
|
depends on HAVE_FSP
|
|
|
|
|
help
|
|
|
|
|
Indicate some buggy FSPs that does not report memory used by FSP
|
|
|
|
|
itself as reserved in the resource descriptor HOB. Select this to
|
|
|
|
|
tell U-Boot to do some additional work to ensure U-Boot relocation
|
|
|
|
|
do not overwrite the important boot service data which is used by
|
|
|
|
|
FSP, otherwise the subsequent call to fsp_notify() will fail.
|
|
|
|
|
|
2015-10-12 04:37:35 +00:00
|
|
|
config ENABLE_MRC_CACHE
|
|
|
|
|
bool "Enable MRC cache"
|
|
|
|
|
depends on !EFI && !SYS_COREBOOT
|
|
|
|
|
help
|
|
|
|
|
Enable this feature to cause MRC data to be cached in NV storage
|
|
|
|
|
to be used for speeding up boot time on future reboots and/or
|
|
|
|
|
power cycles.
|
|
|
|
|
|
2016-05-22 08:45:27 +00:00
|
|
|
For platforms that use Intel FSP for the memory initialization,
|
|
|
|
|
please check FSP output HOB via U-Boot command 'fsp hob' to see
|
|
|
|
|
if there is FSP_NON_VOLATILE_STORAGE_HOB_GUID (asm/fsp/fsp_hob.h).
|
2019-05-03 22:28:37 +00:00
|
|
|
If such GUID does not exist, MRC cache is not available on such
|
2016-05-22 08:45:27 +00:00
|
|
|
platform (eg: Intel Queensbay), which means selecting this option
|
|
|
|
|
here does not make any difference.
|
|
|
|
|
|
2016-03-12 05:07:08 +00:00
|
|
|
config HAVE_MRC
|
|
|
|
|
bool "Add a System Agent binary"
|
|
|
|
|
depends on !HAVE_FSP
|
|
|
|
|
help
|
|
|
|
|
Select this option to add a System Agent binary to
|
|
|
|
|
the resulting U-Boot image. MRC stands for Memory Reference Code.
|
|
|
|
|
It is a binary blob which U-Boot uses to set up SDRAM.
|
|
|
|
|
|
|
|
|
|
Note: Without this binary U-Boot will not be able to set up its
|
|
|
|
|
SDRAM so will not boot.
|
|
|
|
|
|
|
|
|
|
config CACHE_MRC_BIN
|
|
|
|
|
bool
|
|
|
|
|
depends on HAVE_MRC
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Enable caching for the memory reference code binary. This uses an
|
|
|
|
|
MTRR (memory type range register) to turn on caching for the section
|
|
|
|
|
of SPI flash that contains the memory reference code. This makes
|
|
|
|
|
SDRAM init run faster.
|
|
|
|
|
|
|
|
|
|
config CACHE_MRC_SIZE_KB
|
|
|
|
|
int
|
|
|
|
|
depends on HAVE_MRC
|
|
|
|
|
default 512
|
|
|
|
|
help
|
|
|
|
|
Sets the size of the cached area for the memory reference code.
|
|
|
|
|
This ends at the end of SPI flash (address 0xffffffff) and is
|
|
|
|
|
measured in KB. Typically this is set to 512, providing for 0.5MB
|
|
|
|
|
of cached space.
|
|
|
|
|
|
|
|
|
|
config DCACHE_RAM_BASE
|
|
|
|
|
hex
|
|
|
|
|
depends on HAVE_MRC
|
|
|
|
|
help
|
|
|
|
|
Sets the base of the data cache area in memory space. This is the
|
|
|
|
|
start address of the cache-as-RAM (CAR) area and the address varies
|
|
|
|
|
depending on the CPU. Once CAR is set up, read/write memory becomes
|
|
|
|
|
available at this address and can be used temporarily until SDRAM
|
|
|
|
|
is working.
|
|
|
|
|
|
|
|
|
|
config DCACHE_RAM_SIZE
|
|
|
|
|
hex
|
|
|
|
|
depends on HAVE_MRC
|
|
|
|
|
default 0x40000
|
|
|
|
|
help
|
|
|
|
|
Sets the total size of the data cache area in memory space. This
|
|
|
|
|
sets the size of the cache-as-RAM (CAR) area. Note that much of the
|
|
|
|
|
CAR space is required by the MRC. The CAR space available to U-Boot
|
|
|
|
|
is normally at the start and typically extends to 1/4 or 1/2 of the
|
|
|
|
|
available size.
|
|
|
|
|
|
|
|
|
|
config DCACHE_RAM_MRC_VAR_SIZE
|
|
|
|
|
hex
|
|
|
|
|
depends on HAVE_MRC
|
|
|
|
|
help
|
|
|
|
|
This is the amount of CAR (Cache as RAM) reserved for use by the
|
|
|
|
|
memory reference code. This depends on the implementation of the
|
|
|
|
|
memory reference code and must be set correctly or the board will
|
|
|
|
|
not boot.
|
|
|
|
|
|
2016-03-12 05:07:16 +00:00
|
|
|
config HAVE_REFCODE
|
|
|
|
|
bool "Add a Reference Code binary"
|
|
|
|
|
help
|
|
|
|
|
Select this option to add a Reference Code binary to the resulting
|
|
|
|
|
U-Boot image. This is an Intel binary blob that handles system
|
|
|
|
|
initialisation, in this case the PCH and System Agent.
|
|
|
|
|
|
|
|
|
|
Note: Without this binary (on platforms that need it such as
|
|
|
|
|
broadwell) U-Boot will be missing some critical setup steps.
|
|
|
|
|
Various peripherals may fail to work.
|
|
|
|
|
|
2015-04-30 04:25:59 +00:00
|
|
|
config SMP
|
|
|
|
|
bool "Enable Symmetric Multiprocessing"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Enable use of more than one CPU in U-Boot and the Operating System
|
|
|
|
|
when loaded. Each CPU will be started up and information can be
|
|
|
|
|
obtained using the 'cpu' command. If this option is disabled, then
|
|
|
|
|
only one CPU will be enabled regardless of the number of CPUs
|
|
|
|
|
available.
|
|
|
|
|
|
2015-06-12 06:52:23 +00:00
|
|
|
config MAX_CPUS
|
|
|
|
|
int "Maximum number of CPUs permitted"
|
|
|
|
|
depends on SMP
|
|
|
|
|
default 4
|
|
|
|
|
help
|
|
|
|
|
When using multi-CPU chips it is possible for U-Boot to start up
|
|
|
|
|
more than one CPU. The stack memory used by all of these CPUs is
|
|
|
|
|
pre-allocated so at present U-Boot wants to know the maximum
|
|
|
|
|
number of CPUs that may be present. Set this to at least as high
|
|
|
|
|
as the number of CPUs in your system (it uses about 4KB of RAM for
|
|
|
|
|
each CPU).
|
|
|
|
|
|
2015-04-30 04:25:59 +00:00
|
|
|
config AP_STACK_SIZE
|
|
|
|
|
hex
|
2015-06-12 06:52:22 +00:00
|
|
|
depends on SMP
|
2015-04-30 04:25:59 +00:00
|
|
|
default 0x1000
|
|
|
|
|
help
|
|
|
|
|
Each additional CPU started by U-Boot requires its own stack. This
|
|
|
|
|
option sets the stack size used by each CPU and directly affects
|
|
|
|
|
the memory used by this initialisation process. Typically 4KB is
|
|
|
|
|
enough space.
|
|
|
|
|
|
2017-08-17 08:10:42 +00:00
|
|
|
config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
This option indicates that the turbo mode setting is not package
|
|
|
|
|
scoped. i.e. turbo_enable() needs to be called on not just the
|
|
|
|
|
bootstrap processor (BSP).
|
|
|
|
|
|
2015-07-06 08:31:33 +00:00
|
|
|
config HAVE_VGA_BIOS
|
|
|
|
|
bool "Add a VGA BIOS image"
|
|
|
|
|
help
|
|
|
|
|
Select this option if you have a VGA BIOS image that you would
|
|
|
|
|
like to add to your ROM.
|
|
|
|
|
|
|
|
|
|
config VGA_BIOS_FILE
|
|
|
|
|
string "VGA BIOS image filename"
|
|
|
|
|
depends on HAVE_VGA_BIOS
|
|
|
|
|
default "vga.bin"
|
|
|
|
|
help
|
|
|
|
|
The filename of the VGA BIOS image in the board directory.
|
|
|
|
|
|
|
|
|
|
config VGA_BIOS_ADDR
|
|
|
|
|
hex "VGA BIOS image location"
|
|
|
|
|
depends on HAVE_VGA_BIOS
|
|
|
|
|
default 0xfff90000
|
|
|
|
|
help
|
|
|
|
|
The location of VGA BIOS image in the SPI flash. For example, base
|
|
|
|
|
address of 0xfff90000 indicates that the image will be put at offset
|
|
|
|
|
0x90000 from the beginning of a 1MB flash device.
|
|
|
|
|
|
2017-08-16 05:41:53 +00:00
|
|
|
config HAVE_VBT
|
|
|
|
|
bool "Add a Video BIOS Table (VBT) image"
|
|
|
|
|
depends on HAVE_FSP
|
|
|
|
|
help
|
|
|
|
|
Select this option if you have a Video BIOS Table (VBT) image that
|
|
|
|
|
you would like to add to your ROM. This is normally required if you
|
|
|
|
|
are using an Intel FSP firmware that is complaint with spec 1.1 or
|
|
|
|
|
later to initialize the integrated graphics device (IGD).
|
|
|
|
|
|
|
|
|
|
Video BIOS Table, or VBT, provides platform and board specific
|
|
|
|
|
configuration information to the driver that is not discoverable
|
|
|
|
|
or available through other means. By other means the most used
|
|
|
|
|
method here is to read EDID table from the attached monitor, over
|
|
|
|
|
Display Data Channel (DDC) using two pin I2C serial interface. VBT
|
|
|
|
|
configuration is related to display hardware and is available via
|
|
|
|
|
the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
|
|
|
|
|
|
|
|
|
|
config VBT_FILE
|
|
|
|
|
string "Video BIOS Table (VBT) image filename"
|
|
|
|
|
depends on HAVE_VBT
|
|
|
|
|
default "vbt.bin"
|
|
|
|
|
help
|
|
|
|
|
The filename of the file to use as Video BIOS Table (VBT) image
|
|
|
|
|
in the board directory.
|
|
|
|
|
|
|
|
|
|
config VBT_ADDR
|
|
|
|
|
hex "Video BIOS Table (VBT) image location"
|
|
|
|
|
depends on HAVE_VBT
|
|
|
|
|
default 0xfff90000
|
|
|
|
|
help
|
|
|
|
|
The location of Video BIOS Table (VBT) image in the SPI flash. For
|
|
|
|
|
example, base address of 0xfff90000 indicates that the image will
|
|
|
|
|
be put at offset 0x90000 from the beginning of a 1MB flash device.
|
|
|
|
|
|
2017-08-16 05:41:56 +00:00
|
|
|
config VIDEO_FSP
|
|
|
|
|
bool "Enable FSP framebuffer driver support"
|
|
|
|
|
depends on HAVE_VBT && DM_VIDEO
|
|
|
|
|
help
|
|
|
|
|
Turn on this option to enable a framebuffer driver when U-Boot is
|
|
|
|
|
using Video BIOS Table (VBT) image for FSP firmware to initialize
|
|
|
|
|
the integrated graphics device.
|
|
|
|
|
|
2017-07-28 17:02:15 +00:00
|
|
|
config ROM_TABLE_ADDR
|
|
|
|
|
hex
|
|
|
|
|
default 0xf0000
|
|
|
|
|
help
|
|
|
|
|
All x86 tables happen to like the address range from 0x0f0000
|
|
|
|
|
to 0x100000. We use 0xf0000 as the starting address to store
|
|
|
|
|
those tables, including PIRQ routing table, Multi-Processor
|
|
|
|
|
table and ACPI table.
|
|
|
|
|
|
|
|
|
|
config ROM_TABLE_SIZE
|
|
|
|
|
hex
|
|
|
|
|
default 0x10000
|
|
|
|
|
|
2015-04-24 10:10:05 +00:00
|
|
|
menu "System tables"
|
2015-08-13 07:29:13 +00:00
|
|
|
depends on !EFI && !SYS_COREBOOT
|
2015-04-24 10:10:05 +00:00
|
|
|
|
|
|
|
|
config GENERATE_PIRQ_TABLE
|
|
|
|
|
bool "Generate a PIRQ table"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Generate a PIRQ routing table for this board. The PIRQ routing table
|
|
|
|
|
is generated by U-Boot in the system memory from 0xf0000 to 0xfffff
|
|
|
|
|
at every 16-byte boundary with a PCI IRQ routing signature ("$PIR").
|
|
|
|
|
It specifies the interrupt router information as well how all the PCI
|
|
|
|
|
devices' interrupt pins are wired to PIRQs.
|
|
|
|
|
|
2015-04-29 02:25:10 +00:00
|
|
|
config GENERATE_SFI_TABLE
|
|
|
|
|
bool "Generate a SFI (Simple Firmware Interface) table"
|
|
|
|
|
help
|
|
|
|
|
The Simple Firmware Interface (SFI) provides a lightweight method
|
|
|
|
|
for platform firmware to pass information to the operating system
|
|
|
|
|
via static tables in memory. Kernel SFI support is required to
|
|
|
|
|
boot on SFI-only platforms. If you have ACPI tables then these are
|
|
|
|
|
used instead.
|
|
|
|
|
|
|
|
|
|
U-Boot writes this table in write_sfi_table() just before booting
|
|
|
|
|
the OS.
|
|
|
|
|
|
|
|
|
|
For more information, see http://simplefirmware.org
|
|
|
|
|
|
2015-06-23 04:18:52 +00:00
|
|
|
config GENERATE_MP_TABLE
|
|
|
|
|
bool "Generate an MP (Multi-Processor) table"
|
|
|
|
|
default n
|
|
|
|
|
help
|
|
|
|
|
Generate an MP (Multi-Processor) table for this board. The MP table
|
|
|
|
|
provides a way for the operating system to support for symmetric
|
|
|
|
|
multiprocessing as well as symmetric I/O interrupt handling with
|
|
|
|
|
the local APIC and I/O APIC.
|
|
|
|
|
|
x86: Generate a valid ACPI table
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT
ACPI table entries.
Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need
actually write the APCI table just like we did for PIRQ routing, MP table
and SFI tables. With ACPI table existence, linux kernel gets control of
power management, thermal management, configuration management and
monitoring in hardware.
Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tidied up whitespace and aligned some tabs:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-22 06:50:55 +00:00
|
|
|
config GENERATE_ACPI_TABLE
|
|
|
|
|
bool "Generate an ACPI (Advanced Configuration and Power Interface) table"
|
|
|
|
|
default n
|
2016-05-23 02:37:14 +00:00
|
|
|
select QFW if QEMU
|
x86: Generate a valid ACPI table
Implement write_acpi_table() to create a minimal working ACPI table.
This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT
ACPI table entries.
Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need
actually write the APCI table just like we did for PIRQ routing, MP table
and SFI tables. With ACPI table existence, linux kernel gets control of
power management, thermal management, configuration management and
monitoring in hardware.
Signed-off-by: Saket Sinha <saket.sinha89@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tidied up whitespace and aligned some tabs:
Signed-off-by: Simon Glass <sjg@chromium.org>
2015-08-22 06:50:55 +00:00
|
|
|
help
|
|
|
|
|
The Advanced Configuration and Power Interface (ACPI) specification
|
|
|
|
|
provides an open standard for device configuration and management
|
|
|
|
|
by the operating system. It defines platform-independent interfaces
|
|
|
|
|
for configuration and power management monitoring.
|
|
|
|
|
|
2015-04-24 10:10:05 +00:00
|
|
|
endmenu
|
|
|
|
|
|
2017-04-21 14:24:28 +00:00
|
|
|
config HAVE_ACPI_RESUME
|
|
|
|
|
bool "Enable ACPI S3 resume"
|
2017-10-19 01:20:55 +00:00
|
|
|
select ENABLE_MRC_CACHE
|
2017-04-21 14:24:28 +00:00
|
|
|
help
|
|
|
|
|
Select this to enable ACPI S3 resume. S3 is an ACPI-defined sleeping
|
|
|
|
|
state where all system context is lost except system memory. U-Boot
|
|
|
|
|
is responsible for restoring the machine state as it was before sleep.
|
|
|
|
|
It needs restore the memory controller, without overwriting memory
|
|
|
|
|
which is not marked as reserved. For the peripherals which lose their
|
|
|
|
|
registers, U-Boot needs to write the original value. When everything
|
|
|
|
|
is done, U-Boot needs to find out the wakeup vector provided by OSes
|
|
|
|
|
and jump there.
|
|
|
|
|
|
2017-04-21 14:24:46 +00:00
|
|
|
config S3_VGA_ROM_RUN
|
|
|
|
|
bool "Re-run VGA option ROMs on S3 resume"
|
|
|
|
|
depends on HAVE_ACPI_RESUME
|
|
|
|
|
help
|
|
|
|
|
Execute VGA option ROMs in U-Boot when resuming from S3. Normally
|
|
|
|
|
this is needed when graphics console is being used in the kernel.
|
|
|
|
|
|
|
|
|
|
Turning it off can reduce some resume time, but be aware that your
|
|
|
|
|
graphics console won't work without VGA options ROMs. Set it to N
|
|
|
|
|
if your kernel is only on a serial console.
|
|
|
|
|
|
2017-04-21 14:24:34 +00:00
|
|
|
config STACK_SIZE
|
|
|
|
|
hex
|
|
|
|
|
depends on HAVE_ACPI_RESUME
|
|
|
|
|
default 0x1000
|
|
|
|
|
help
|
|
|
|
|
Estimated U-Boot's runtime stack size that needs to be reserved
|
|
|
|
|
during an ACPI S3 resume.
|
|
|
|
|
|
2015-04-24 10:10:05 +00:00
|
|
|
config MAX_PIRQ_LINKS
|
|
|
|
|
int
|
|
|
|
|
default 8
|
|
|
|
|
help
|
|
|
|
|
This variable specifies the number of PIRQ interrupt links which are
|
|
|
|
|
routable. On most older chipsets, this is 4, PIRQA through PIRQD.
|
|
|
|
|
Some newer chipsets offer more than four links, commonly up to PIRQH.
|
|
|
|
|
|
|
|
|
|
config IRQ_SLOT_COUNT
|
|
|
|
|
int
|
|
|
|
|
default 128
|
|
|
|
|
help
|
|
|
|
|
U-Boot can support up to 254 IRQ slot info in the PIRQ routing table
|
|
|
|
|
which in turns forms a table of exact 4KiB. The default value 128
|
|
|
|
|
should be enough for most boards. If this does not fit your board,
|
|
|
|
|
change it according to your needs.
|
|
|
|
|
|
2015-01-28 05:13:33 +00:00
|
|
|
config PCIE_ECAM_BASE
|
|
|
|
|
hex
|
2015-02-02 13:25:09 +00:00
|
|
|
default 0xe0000000
|
2015-01-28 05:13:33 +00:00
|
|
|
help
|
|
|
|
|
This is the memory-mapped address of PCI configuration space, which
|
|
|
|
|
is only available through the Enhanced Configuration Access
|
|
|
|
|
Mechanism (ECAM) with PCI Express. It can be set up almost
|
|
|
|
|
anywhere. Before it is set up, it is possible to access PCI
|
|
|
|
|
configuration space through I/O access, but memory access is more
|
|
|
|
|
convenient. Using this, PCI can be scanned and configured. This
|
|
|
|
|
should be set to a region that does not conflict with memory
|
|
|
|
|
assigned to PCI devices - i.e. the memory and prefetch regions, as
|
|
|
|
|
passed to pci_set_region().
|
|
|
|
|
|
2015-07-22 08:21:15 +00:00
|
|
|
config PCIE_ECAM_SIZE
|
|
|
|
|
hex
|
|
|
|
|
default 0x10000000
|
|
|
|
|
help
|
|
|
|
|
This is the size of memory-mapped address of PCI configuration space,
|
|
|
|
|
which is only available through the Enhanced Configuration Access
|
|
|
|
|
Mechanism (ECAM) with PCI Express. Each bus consumes 1 MiB memory,
|
|
|
|
|
so a default 0x10000000 size covers all of the 256 buses which is the
|
|
|
|
|
maximum number of PCI buses as defined by the PCI specification.
|
|
|
|
|
|
2015-10-23 02:13:31 +00:00
|
|
|
config I8259_PIC
|
2018-11-30 03:57:22 +00:00
|
|
|
bool "Enable Intel 8259 compatible interrupt controller"
|
2015-10-23 02:13:31 +00:00
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Intel 8259 ISA compatible chipset incorporates two 8259 (master and
|
|
|
|
|
slave) interrupt controllers. Include this to have U-Boot set up
|
|
|
|
|
the interrupt correctly.
|
|
|
|
|
|
2018-11-18 22:19:43 +00:00
|
|
|
config APIC
|
2018-11-30 03:57:22 +00:00
|
|
|
bool "Enable Intel Advanced Programmable Interrupt Controller"
|
2018-11-18 22:19:43 +00:00
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
The (A)dvanced (P)rogrammable (I)nterrupt (C)ontroller is responsible
|
|
|
|
|
for catching interrupts and distributing them to one or more CPU
|
|
|
|
|
cores. In most cases there are some LAPICs (local) for each core and
|
|
|
|
|
one I/O APIC. This conjunction is found on most modern x86 systems.
|
|
|
|
|
|
2018-06-10 13:25:01 +00:00
|
|
|
config PINCTRL_ICH6
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Intel ICH6 compatible chipset pinctrl driver. It needs to work
|
|
|
|
|
together with the ICH6 compatible gpio driver.
|
|
|
|
|
|
2015-10-23 02:13:31 +00:00
|
|
|
config I8254_TIMER
|
|
|
|
|
bool
|
|
|
|
|
default y
|
|
|
|
|
help
|
|
|
|
|
Intel 8254 timer contains three counters which have fixed uses.
|
|
|
|
|
Include this to have U-Boot set up the timer correctly.
|
|
|
|
|
|
2016-02-29 07:54:50 +00:00
|
|
|
config SEABIOS
|
|
|
|
|
bool "Support booting SeaBIOS"
|
|
|
|
|
help
|
|
|
|
|
SeaBIOS is an open source implementation of a 16-bit X86 BIOS.
|
|
|
|
|
It can run in an emulator or natively on X86 hardware with the use
|
|
|
|
|
of coreboot/U-Boot. By turning on this option, U-Boot prepares
|
|
|
|
|
all the configuration tables that are necessary to boot SeaBIOS.
|
|
|
|
|
|
|
|
|
|
Check http://www.seabios.org/SeaBIOS for details.
|
|
|
|
|
|
2016-05-11 14:44:59 +00:00
|
|
|
config HIGH_TABLE_SIZE
|
|
|
|
|
hex "Size of configuration tables which reside in high memory"
|
|
|
|
|
default 0x10000
|
|
|
|
|
depends on SEABIOS
|
|
|
|
|
help
|
|
|
|
|
SeaBIOS itself resides in E seg and F seg, where U-Boot puts all
|
|
|
|
|
configuration tables like PIRQ/MP/ACPI. To avoid conflicts, U-Boot
|
|
|
|
|
puts a copy of configuration tables in high memory region which
|
|
|
|
|
is reserved on the stack before relocation. The region size is
|
|
|
|
|
determined by this option.
|
|
|
|
|
|
|
|
|
|
Increse it if the default size does not fit the board's needs.
|
|
|
|
|
This is most likely due to a large ACPI DSDT table is used.
|
|
|
|
|
|
2014-07-30 05:08:14 +00:00
|
|
|
endmenu
|
