2015-06-05 09:59:02 +00:00
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CONFIG_PPC=y
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2018-02-03 17:10:38 +00:00
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CONFIG_SYS_TEXT_BASE=0x30001000
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2016-09-13 05:18:41 +00:00
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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2016-09-13 05:18:43 +00:00
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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2019-11-19 01:02:10 +00:00
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x100000
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2020-04-28 20:15:47 +00:00
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CONFIG_ENV_SECT_SIZE=0x10000
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2021-06-28 14:17:29 +00:00
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CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb"
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2020-07-06 17:54:25 +00:00
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CONFIG_SPL_TEXT_BASE=0xFFFD8000
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2021-08-08 18:20:12 +00:00
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CONFIG_SPL_SERIAL=y
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2021-07-11 03:14:31 +00:00
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CONFIG_SPL_DRIVERS_MISC=y
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2018-06-04 15:57:37 +00:00
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CONFIG_SPL=y
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2016-09-13 05:18:57 +00:00
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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2021-08-08 18:20:14 +00:00
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CONFIG_SPL_SPI=y
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2015-06-05 09:59:02 +00:00
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CONFIG_MPC85xx=y
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2016-11-21 19:04:34 +00:00
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CONFIG_TARGET_T1042D4RDB=y
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2022-01-24 21:08:41 +00:00
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CONFIG_MP=y
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2016-02-23 05:55:43 +00:00
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
|
2021-08-25 03:11:49 +00:00
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|
CONFIG_RAMBOOT_PBL=y
|
2022-03-23 21:20:03 +00:00
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|
|
CONFIG_SPIFLASH=y
|
2021-08-25 03:11:49 +00:00
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|
|
CONFIG_SYS_FSL_PBL_PBI="$(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg"
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CONFIG_SYS_FSL_PBL_RCW="$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg"
|
2016-06-07 06:31:14 +00:00
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|
|
CONFIG_BOOTDELAY=10
|
2021-11-10 14:11:40 +00:00
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|
|
CONFIG_USE_BOOTCOMMAND=y
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|
|
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/ram rw console=$consoledev,$baudrate $othbootargs;setenv ramdiskaddr 0x02000000;setenv fdtaddr 0x00c00000;setenv loadaddr 0x1000000;bootm $loadaddr $ramdiskaddr $fdtaddr"
|
2016-10-18 02:12:35 +00:00
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|
|
CONFIG_SILENT_CONSOLE=y
|
2016-10-18 02:12:37 +00:00
|
|
|
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
2017-01-23 20:31:20 +00:00
|
|
|
CONFIG_BOARD_EARLY_INIT_F=y
|
2018-03-28 12:38:15 +00:00
|
|
|
CONFIG_BOARD_EARLY_INIT_R=y
|
2018-02-06 17:15:38 +00:00
|
|
|
# CONFIG_SPL_FRAMEWORK is not set
|
2019-06-01 18:20:25 +00:00
|
|
|
CONFIG_SPL_SPI_BOOT=y
|
|
|
|
CONFIG_SPL_FSL_PBL=y
|
2017-03-13 17:48:42 +00:00
|
|
|
CONFIG_SPL_ENV_SUPPORT=y
|
2021-07-11 03:14:36 +00:00
|
|
|
CONFIG_SPL_I2C=y
|
2021-08-08 18:20:16 +00:00
|
|
|
CONFIG_SPL_MPC8XXX_INIT_DDR=y
|
2016-04-22 01:37:19 +00:00
|
|
|
CONFIG_HUSH_PARSER=y
|
2017-10-08 18:48:01 +00:00
|
|
|
CONFIG_CMD_IMLS=y
|
2016-04-24 21:29:26 +00:00
|
|
|
CONFIG_CMD_GREPENV=y
|
2021-04-13 16:48:05 +00:00
|
|
|
CONFIG_CMD_DM=y
|
2017-08-14 23:58:53 +00:00
|
|
|
CONFIG_CMD_I2C=y
|
2016-04-24 21:29:26 +00:00
|
|
|
CONFIG_CMD_MMC=y
|
2016-04-22 20:41:25 +00:00
|
|
|
CONFIG_CMD_USB=y
|
|
|
|
CONFIG_CMD_DHCP=y
|
2016-04-24 21:29:26 +00:00
|
|
|
CONFIG_CMD_MII=y
|
2016-04-22 20:41:25 +00:00
|
|
|
CONFIG_CMD_PING=y
|
2016-04-24 21:29:26 +00:00
|
|
|
CONFIG_CMD_EXT2=y
|
|
|
|
CONFIG_CMD_FAT=y
|
2017-10-22 21:55:07 +00:00
|
|
|
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
|
|
|
|
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
|
2019-08-20 09:35:27 +00:00
|
|
|
CONFIG_OF_CONTROL=y
|
2020-07-03 11:48:56 +00:00
|
|
|
CONFIG_ENV_OVERWRITE=y
|
2017-08-28 11:16:32 +00:00
|
|
|
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
2022-02-25 16:19:48 +00:00
|
|
|
CONFIG_USE_BOOTFILE=y
|
|
|
|
CONFIG_BOOTFILE="uImage"
|
2022-03-11 14:12:07 +00:00
|
|
|
CONFIG_USE_ETHPRIME=y
|
|
|
|
CONFIG_ETHPRIME="FM1@DTSEC4"
|
2019-09-23 15:47:37 +00:00
|
|
|
CONFIG_DM=y
|
2017-03-01 21:51:58 +00:00
|
|
|
CONFIG_FSL_CAAM=y
|
2021-08-21 17:50:17 +00:00
|
|
|
CONFIG_DDR_CLK_FREQ=66666666
|
2022-02-25 16:19:53 +00:00
|
|
|
CONFIG_CHIP_SELECTS_PER_CTRL=2
|
2021-08-21 17:50:18 +00:00
|
|
|
CONFIG_DDR_ECC=y
|
|
|
|
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
|
2020-05-08 13:08:39 +00:00
|
|
|
CONFIG_DM_I2C=y
|
2021-08-19 03:12:24 +00:00
|
|
|
CONFIG_SPL_SYS_I2C_LEGACY=y
|
2021-08-19 03:12:37 +00:00
|
|
|
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
2021-08-19 03:12:35 +00:00
|
|
|
CONFIG_SYS_I2C_FSL=y
|
|
|
|
CONFIG_SYS_FSL_I2C_OFFSET=0x118000
|
|
|
|
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
|
|
|
|
CONFIG_SYS_FSL_I2C2_OFFSET=0x118100
|
|
|
|
CONFIG_SYS_FSL_HAS_I2C3_OFFSET=y
|
|
|
|
CONFIG_SYS_FSL_I2C3_OFFSET=0x119000
|
|
|
|
CONFIG_SYS_FSL_HAS_I2C4_OFFSET=y
|
|
|
|
CONFIG_SYS_FSL_I2C4_OFFSET=0x119100
|
2018-03-28 12:38:19 +00:00
|
|
|
CONFIG_FSL_ESDHC=y
|
2019-12-04 22:18:38 +00:00
|
|
|
CONFIG_MTD=y
|
2018-10-14 20:10:50 +00:00
|
|
|
CONFIG_MTD_NOR_FLASH=y
|
|
|
|
CONFIG_FLASH_CFI_DRIVER=y
|
|
|
|
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|
|
|
CONFIG_FLASH_CFI_MTD=y
|
|
|
|
CONFIG_SYS_FLASH_CFI=y
|
2022-01-04 13:24:00 +00:00
|
|
|
CONFIG_SYS_MAX_FLASH_BANKS=2
|
2020-10-05 17:11:41 +00:00
|
|
|
CONFIG_DM_SPI_FLASH=y
|
2019-02-27 14:20:36 +00:00
|
|
|
CONFIG_SF_DEFAULT_SPEED=10000000
|
2015-11-25 13:34:54 +00:00
|
|
|
CONFIG_SPI_FLASH_STMICRO=y
|
2017-08-02 00:19:59 +00:00
|
|
|
CONFIG_PHYLIB=y
|
2020-04-24 19:35:53 +00:00
|
|
|
CONFIG_PHY_REALTEK=y
|
|
|
|
CONFIG_PHY_VITESSE=y
|
2021-04-13 16:48:05 +00:00
|
|
|
CONFIG_DM_ETH=y
|
|
|
|
CONFIG_DM_MDIO=y
|
2017-08-08 02:00:34 +00:00
|
|
|
CONFIG_PHY_GIGE=y
|
2015-08-19 15:33:43 +00:00
|
|
|
CONFIG_E1000=y
|
2019-09-23 15:47:37 +00:00
|
|
|
CONFIG_FMAN_ENET=y
|
2021-11-09 11:00:38 +00:00
|
|
|
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
2019-09-23 15:47:37 +00:00
|
|
|
CONFIG_MII=y
|
2019-08-27 11:03:54 +00:00
|
|
|
CONFIG_PCIE_FSL=y
|
2021-12-11 19:55:51 +00:00
|
|
|
CONFIG_U_QE=y
|
2021-11-12 23:37:42 +00:00
|
|
|
CONFIG_SYS_QE_FW_ADDR=0x130000
|
2019-05-12 11:59:12 +00:00
|
|
|
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
|
2020-05-08 13:08:39 +00:00
|
|
|
CONFIG_DM_RTC=y
|
2015-11-19 13:48:14 +00:00
|
|
|
CONFIG_SYS_NS16550=y
|
2018-04-15 17:51:26 +00:00
|
|
|
CONFIG_SPI=y
|
2020-10-05 17:11:41 +00:00
|
|
|
CONFIG_DM_SPI=y
|
2015-11-25 13:34:53 +00:00
|
|
|
CONFIG_FSL_ESPI=y
|
2016-09-08 20:31:26 +00:00
|
|
|
CONFIG_USB=y
|
2021-12-11 19:55:51 +00:00
|
|
|
CONFIG_USB_EHCI_FSL=y
|
2020-10-05 17:11:41 +00:00
|
|
|
CONFIG_USB_STORAGE=y
|
2020-06-03 12:43:40 +00:00
|
|
|
CONFIG_ADDR_MAP=y
|
|
|
|
CONFIG_SYS_NUM_ADDR_MAP=64
|