2018-05-06 21:58:06 +00:00
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/* SPDX-License-Identifier: GPL-2.0+ */
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2014-06-23 22:15:54 +00:00
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/*
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2015-10-26 11:47:50 +00:00
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* (C) Copyright 2014-2015 Freescale Semiconductor
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armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-28 16:07:58 +00:00
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* Copyright 2019 NXP
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2014-06-23 22:15:54 +00:00
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*
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* Extracted from armv8/start.S
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*/
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#include <config.h>
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#include <linux/linkage.h>
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2014-09-08 19:20:00 +00:00
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#include <asm/gic.h>
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2014-06-23 22:15:54 +00:00
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#include <asm/macro.h>
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2017-01-17 10:31:15 +00:00
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#include <asm/arch-fsl-layerscape/soc.h>
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2016-11-17 06:59:51 +00:00
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#ifdef CONFIG_FSL_LSCH3
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#include <asm/arch-fsl-layerscape/immap_lsch3.h>
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#endif
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2016-11-10 02:49:03 +00:00
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#include <asm/u-boot.h>
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2014-06-23 22:15:54 +00:00
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2020-06-01 19:53:27 +00:00
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.align 3
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.weak secondary_boot_addr
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secondary_boot_addr:
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.quad 0
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2017-01-17 10:31:15 +00:00
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/* Get GIC offset
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* For LS1043a rev1.0, GIC base address align with 4k.
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* For LS1043a rev1.1, if DCFG_GIC400_ALIGN[GIC_ADDR_BIT]
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* is set, GIC base address align with 4K, or else align
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* with 64k.
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* output:
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* x0: the base address of GICD
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* x1: the base address of GICC
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*/
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ENTRY(get_gic_offset)
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ldr x0, =GICD_BASE
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#ifdef CONFIG_GICV2
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ldr x1, =GICC_BASE
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#endif
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#ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
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ldr x2, =DCFG_CCSR_SVR
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ldr w2, [x2]
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rev w2, w2
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2017-12-04 04:18:28 +00:00
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lsr w3, w2, #16
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ldr w4, =SVR_DEV(SVR_LS1043A)
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2017-01-17 10:31:15 +00:00
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cmp w3, w4
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b.ne 1f
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ands w2, w2, #0xff
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cmp w2, #REV1_0
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b.eq 1f
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ldr x2, =SCFG_GIC400_ALIGN
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ldr w2, [x2]
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rev w2, w2
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tbnz w2, #GIC_ADDR_BIT, 1f
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ldr x0, =GICD_BASE_64K
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#ifdef CONFIG_GICV2
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ldr x1, =GICC_BASE_64K
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#endif
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1:
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#endif
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ret
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ENDPROC(get_gic_offset)
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ENTRY(smp_kick_all_cpus)
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/* Kick secondary cpus up by SGI 0 interrupt */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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mov x29, lr /* Save LR */
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bl get_gic_offset
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bl gic_kick_secondary_cpus
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mov lr, x29 /* Restore LR */
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#endif
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ret
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ENDPROC(smp_kick_all_cpus)
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2014-06-23 22:15:54 +00:00
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ENTRY(lowlevel_init)
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mov x29, lr /* Save LR */
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2017-05-15 15:51:59 +00:00
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switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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1:
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2017-08-18 05:24:36 +00:00
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#if defined (CONFIG_SYS_FSL_HAS_CCN504)
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2016-01-25 06:38:45 +00:00
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/* Set Wuo bit for RN-I 20 */
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2017-03-27 18:41:01 +00:00
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#ifdef CONFIG_ARCH_LS2080A
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2016-01-25 06:38:45 +00:00
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ldr x0, =CCI_AUX_CONTROL_BASE(20)
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ldr x1, =0x00000010
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bl ccn504_set_aux
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2016-11-09 06:57:54 +00:00
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/*
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* Set forced-order mode in RNI-6, RNI-20
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* This is required for performance optimization on LS2088A
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* LS2080A family does not support setting forced-order mode,
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* so skip this operation for LS2080A family
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*/
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bl get_svr
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lsr w0, w0, #16
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2017-12-04 04:18:28 +00:00
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ldr w1, =SVR_DEV(SVR_LS2080A)
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2016-11-09 06:57:54 +00:00
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cmp w0, w1
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b.eq 1f
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ldr x0, =CCI_AUX_CONTROL_BASE(6)
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ldr x1, =0x00000020
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bl ccn504_set_aux
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ldr x0, =CCI_AUX_CONTROL_BASE(20)
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ldr x1, =0x00000020
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bl ccn504_set_aux
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1:
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2016-01-25 06:38:45 +00:00
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#endif
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2015-03-21 02:28:10 +00:00
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/* Add fully-coherent masters to DVM domain */
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2015-07-01 04:28:03 +00:00
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ldr x0, =CCI_MN_BASE
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ldr x1, =CCI_MN_RNF_NODEID_LIST
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ldr x2, =CCI_MN_DVM_DOMAIN_CTL_SET
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bl ccn504_add_masters_to_dvm
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/* Set all RN-I ports to QoS of 15 */
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(0)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(2)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(6)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(12)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(16)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S0_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S1_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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ldr x0, =CCI_S2_QOS_CONTROL_BASE(20)
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ldr x1, =0x00FF000C
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bl ccn504_set_qos
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2017-08-18 05:24:36 +00:00
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#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
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2015-03-21 02:28:10 +00:00
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2016-06-03 13:11:26 +00:00
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#ifdef SMMU_BASE
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2014-06-23 22:15:54 +00:00
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/* Set the SMMU page size in the sACR register */
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ldr x1, =SMMU_BASE
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ldr w0, [x1, #0x10]
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orr w0, w0, #1 << 16 /* set sACR.pagesize to indicate 64K page */
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str w0, [x1, #0x10]
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2016-06-03 13:11:26 +00:00
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#endif
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2014-06-23 22:15:54 +00:00
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/* Initialize GIC Secure Bank Status */
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2020-11-18 16:45:59 +00:00
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#if !defined(CONFIG_SPL_BUILD)
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2014-06-23 22:15:54 +00:00
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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2017-01-17 10:31:15 +00:00
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bl get_gic_offset
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2014-06-23 22:15:54 +00:00
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bl gic_init_secure
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1:
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#ifdef CONFIG_GICV3
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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2017-01-17 10:31:15 +00:00
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bl get_gic_offset
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2014-06-23 22:15:54 +00:00
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bl gic_init_secure_percpu
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#endif
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#endif
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2020-11-18 16:45:59 +00:00
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#endif
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2014-06-23 22:15:54 +00:00
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2017-05-15 15:51:59 +00:00
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100:
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armv8: Fix and simplify branch_if_master/branch_if_slave
The branch_if_master macro jumps to a label if the CPU is the "master"
core, which we define as having all affinity levels set to 0. To check
for this condition, we need to mask off some bits from the MPIDR
register, then compare the remaining register value against zero.
The implementation of this was slighly broken (it preserved the upper
RES0 bits), overly complicated and hard to understand, especially since
it lacked comments. The same was true for the very similar
branch_if_slave macro.
Use a much shorter assembly sequence for those checks, use the same
masking for both macros (just negate the final branch), and put some
comments on them, to make it clear what the code does.
This allows to drop the second temporary register for branch_if_master,
so we adjust all call sites as well.
Also use the opportunity to remove a misleading comment: the macro
works fine on SoCs with multiple clusters. Judging by the commit
message, the original problem with the Juno SoC stems from the fact that
the master CPU *can* be configured to be from cluster 1, so the
assumption that the master CPU has all affinity values set to 0 does not
hold there. But this is already mentioned above in a comment, so remove
the extra comment.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-11 11:29:39 +00:00
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branch_if_master x0, 2f
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2014-06-23 22:15:54 +00:00
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2015-10-26 11:47:50 +00:00
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#if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
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2020-06-01 19:53:26 +00:00
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/*
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* Formerly, here was a jump to secondary_boot_func, but we just
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* return early here and let the generic code in start.S handle
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* the jump to secondary_boot_func.
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*/
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mov lr, x29 /* Restore LR */
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ret
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2015-10-26 11:47:50 +00:00
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#endif
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2015-01-06 21:11:21 +00:00
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2015-10-26 11:47:50 +00:00
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2:
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2017-05-15 15:51:59 +00:00
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switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
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1:
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2015-01-06 21:11:21 +00:00
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#ifdef CONFIG_FSL_TZPC_BP147
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/* Set Non Secure access for all devices protected via TZPC */
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ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */
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orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */
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str w0, [x1]
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isb
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dsb sy
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#endif
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#ifdef CONFIG_FSL_TZASC_400
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2016-11-17 06:59:54 +00:00
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/*
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* LS2080 and its personalities does not support TZASC
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* So skip TZASC related operations
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*/
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bl get_svr
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lsr w0, w0, #16
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2017-12-04 04:18:28 +00:00
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ldr w1, =SVR_DEV(SVR_LS2080A)
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2016-11-17 06:59:54 +00:00
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cmp w0, w1
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b.eq 1f
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2015-01-06 21:11:21 +00:00
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/* Set TZASC so that:
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* a. We use only Region0 whose global secure write/read is EN
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* b. We use only Region0 whose NSAID write/read is EN
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*
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* NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
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2021-09-27 15:42:39 +00:00
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* placeholders.
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2015-01-06 21:11:21 +00:00
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*/
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2018-03-26 08:52:43 +00:00
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.macro tzasc_prog, xreg
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mov x12, TZASC1_BASE
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mov x16, #0x10000
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mul x14, \xreg, x16
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add x14, x14,x12
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2021-09-27 15:42:39 +00:00
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mov x1, #0x8
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2018-03-26 08:52:43 +00:00
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add x1, x1, x14
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ldr w0, [x1] /* Filter 0 Gate Keeper Register */
|
|
|
|
|
orr w0, w0, #1 << 0 /* Set open_request for Filter 0 */
|
|
|
|
|
str w0, [x1]
|
|
|
|
|
|
|
|
|
|
mov x1, #0x110
|
|
|
|
|
add x1, x1, x14
|
|
|
|
|
|
|
|
|
|
ldr w0, [x1] /* Region-0 Attributes Register */
|
|
|
|
|
orr w0, w0, #1 << 31 /* Set Sec global write en, Bit[31] */
|
|
|
|
|
orr w0, w0, #1 << 30 /* Set Sec global read en, Bit[30] */
|
|
|
|
|
str w0, [x1]
|
|
|
|
|
|
|
|
|
|
mov x1, #0x114
|
|
|
|
|
add x1, x1, x14
|
|
|
|
|
|
|
|
|
|
ldr w0, [x1] /* Region-0 Access Register */
|
|
|
|
|
mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */
|
|
|
|
|
str w0, [x1]
|
|
|
|
|
.endm
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_FSL_TZASC_1
|
|
|
|
|
mov x13, #0
|
|
|
|
|
tzasc_prog x13
|
2015-01-06 21:11:21 +00:00
|
|
|
|
2017-04-07 06:10:32 +00:00
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_FSL_TZASC_2
|
2018-03-26 08:52:43 +00:00
|
|
|
mov x13, #1
|
|
|
|
|
tzasc_prog x13
|
2015-01-06 21:11:21 +00:00
|
|
|
|
2017-04-07 06:10:32 +00:00
|
|
|
#endif
|
2015-01-06 21:11:21 +00:00
|
|
|
isb
|
|
|
|
|
dsb sy
|
|
|
|
|
#endif
|
2017-05-15 15:51:59 +00:00
|
|
|
100:
|
2016-11-17 06:59:54 +00:00
|
|
|
1:
|
2016-09-26 15:09:24 +00:00
|
|
|
#ifdef CONFIG_ARCH_LS1046A
|
2017-05-15 15:51:59 +00:00
|
|
|
switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
|
|
|
|
|
1:
|
2016-09-07 09:56:08 +00:00
|
|
|
/* Initialize the L2 RAM latency */
|
|
|
|
|
mrs x1, S3_1_c11_c0_2
|
|
|
|
|
mov x0, #0x1C7
|
|
|
|
|
/* Clear L2 Tag RAM latency and L2 Data RAM latency */
|
|
|
|
|
bic x1, x1, x0
|
|
|
|
|
/* Set L2 data ram latency bits [2:0] */
|
|
|
|
|
orr x1, x1, #0x2
|
|
|
|
|
/* set L2 tag ram latency bits [8:6] */
|
|
|
|
|
orr x1, x1, #0x80
|
|
|
|
|
msr S3_1_c11_c0_2, x1
|
|
|
|
|
isb
|
2017-05-15 15:51:59 +00:00
|
|
|
100:
|
2016-09-07 09:56:08 +00:00
|
|
|
#endif
|
|
|
|
|
|
2018-11-05 18:02:05 +00:00
|
|
|
#if !defined(CONFIG_TFABOOT) && \
|
|
|
|
|
(defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD))
|
2016-12-16 09:15:46 +00:00
|
|
|
bl fsl_ocram_init
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-09-08 19:20:00 +00:00
|
|
|
mov lr, x29 /* Restore LR */
|
|
|
|
|
ret
|
|
|
|
|
ENDPROC(lowlevel_init)
|
|
|
|
|
|
2016-12-16 09:15:46 +00:00
|
|
|
#if defined(CONFIG_FSL_LSCH2) && !defined(CONFIG_SPL_BUILD)
|
|
|
|
|
ENTRY(fsl_ocram_init)
|
|
|
|
|
mov x28, lr /* Save LR */
|
|
|
|
|
bl fsl_clear_ocram
|
|
|
|
|
bl fsl_ocram_clear_ecc_err
|
|
|
|
|
mov lr, x28 /* Restore LR */
|
|
|
|
|
ret
|
|
|
|
|
ENDPROC(fsl_ocram_init)
|
|
|
|
|
|
|
|
|
|
ENTRY(fsl_clear_ocram)
|
|
|
|
|
/* Clear OCRAM */
|
|
|
|
|
ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
|
|
|
|
|
ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
|
|
|
|
|
mov x2, #0
|
|
|
|
|
clear_loop:
|
|
|
|
|
str x2, [x0]
|
|
|
|
|
add x0, x0, #8
|
|
|
|
|
cmp x0, x1
|
|
|
|
|
b.lo clear_loop
|
|
|
|
|
ret
|
|
|
|
|
ENDPROC(fsl_clear_ocram)
|
|
|
|
|
|
|
|
|
|
ENTRY(fsl_ocram_clear_ecc_err)
|
|
|
|
|
/* OCRAM1/2 ECC status bit */
|
|
|
|
|
mov w1, #0x60
|
|
|
|
|
ldr x0, =DCSR_DCFG_SBEESR2
|
|
|
|
|
str w1, [x0]
|
|
|
|
|
ldr x0, =DCSR_DCFG_MBEESR2
|
|
|
|
|
str w1, [x0]
|
|
|
|
|
ret
|
|
|
|
|
ENDPROC(fsl_ocram_init)
|
|
|
|
|
#endif
|
|
|
|
|
|
2016-06-03 13:11:31 +00:00
|
|
|
#ifdef CONFIG_FSL_LSCH3
|
2016-11-17 06:59:51 +00:00
|
|
|
.globl get_svr
|
|
|
|
|
get_svr:
|
|
|
|
|
ldr x1, =FSL_LSCH3_SVR
|
|
|
|
|
ldr w0, [x1]
|
|
|
|
|
ret
|
2017-08-18 05:24:36 +00:00
|
|
|
#endif
|
2016-11-17 06:59:51 +00:00
|
|
|
|
armv8: lx2160a: Add LX2160A SoC Support
LX2160A Soc is based on Layerscape Chassis Generation 3.2
architecture with features:
16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC,
2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers,
3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs,
4 TZASC instances, etc.
SoC personalites:
LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs
LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs
Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2018-10-29 09:17:09 +00:00
|
|
|
#if defined(CONFIG_SYS_FSL_HAS_CCN504) || defined(CONFIG_SYS_FSL_HAS_CCN508)
|
2015-01-06 21:18:42 +00:00
|
|
|
hnf_pstate_poll:
|
armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-28 16:07:58 +00:00
|
|
|
/* x0 has the desired status, return only if operation succeed
|
|
|
|
|
* clobber x1, x2, x6
|
2015-01-06 21:18:42 +00:00
|
|
|
*/
|
|
|
|
|
mov x1, x0
|
armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-28 16:07:58 +00:00
|
|
|
mov w6, #8 /* HN-F node count */
|
2015-01-06 21:18:42 +00:00
|
|
|
mov x0, #0x18
|
|
|
|
|
movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */
|
|
|
|
|
1:
|
|
|
|
|
ldr x2, [x0]
|
|
|
|
|
cmp x2, x1 /* check status */
|
|
|
|
|
b.eq 2f
|
armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-28 16:07:58 +00:00
|
|
|
b 1b
|
2015-01-06 21:18:42 +00:00
|
|
|
2:
|
|
|
|
|
add x0, x0, #0x10000 /* move to next node */
|
|
|
|
|
subs w6, w6, #1
|
|
|
|
|
cbnz w6, 1b
|
|
|
|
|
ret
|
|
|
|
|
|
|
|
|
|
hnf_set_pstate:
|
|
|
|
|
/* x0 has the desired state, clobber x1, x2, x6 */
|
|
|
|
|
mov x1, x0
|
|
|
|
|
/* power state to SFONLY */
|
|
|
|
|
mov w6, #8 /* HN-F node count */
|
|
|
|
|
mov x0, #0x10
|
|
|
|
|
movk x0, #0x420, lsl #16 /* HNF0_PSTATE_REQ */
|
|
|
|
|
1: /* set pstate to sfonly */
|
|
|
|
|
ldr x2, [x0]
|
|
|
|
|
and x2, x2, #0xfffffffffffffffc /* & HNFPSTAT_MASK */
|
|
|
|
|
orr x2, x2, x1
|
|
|
|
|
str x2, [x0]
|
|
|
|
|
add x0, x0, #0x10000 /* move to next node */
|
|
|
|
|
subs w6, w6, #1
|
|
|
|
|
cbnz w6, 1b
|
|
|
|
|
|
|
|
|
|
ret
|
|
|
|
|
|
2016-10-19 21:18:46 +00:00
|
|
|
ENTRY(__asm_flush_l3_dcache)
|
2015-01-06 21:18:42 +00:00
|
|
|
/*
|
|
|
|
|
* Return status in x0
|
|
|
|
|
* success 0
|
|
|
|
|
*/
|
|
|
|
|
mov x29, lr
|
|
|
|
|
|
|
|
|
|
dsb sy
|
|
|
|
|
mov x0, #0x1 /* HNFPSTAT_SFONLY */
|
|
|
|
|
bl hnf_set_pstate
|
|
|
|
|
|
|
|
|
|
mov x0, #0x4 /* SFONLY status */
|
|
|
|
|
bl hnf_pstate_poll
|
armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-28 16:07:58 +00:00
|
|
|
|
2015-01-06 21:18:42 +00:00
|
|
|
dsb sy
|
|
|
|
|
mov x0, #0x3 /* HNFPSTAT_FAM */
|
|
|
|
|
bl hnf_set_pstate
|
|
|
|
|
|
|
|
|
|
mov x0, #0xc /* FAM status */
|
|
|
|
|
bl hnf_pstate_poll
|
armv8/fsl-layerscape: Add loop to check L3 dcache status
Flushing L3 cache may need variable time depending upon cache line
allocation.
Coming up with a proper timeout value would be best handled by
simulations under multiple scenarios in your actual system.
>From the purely HN-F point of view, the flush would take ~15 cycles for
a clean line, and ~22 cycles for a dirty line. For the dirty line case,
there are many variables outside the HN-F that will increase the
duration per line. For example, a *DBIDResp from the SN-F/SBSX,
memory controller latency, SN-F/SBSX RetryAck responses, CCN ring
congestion, CCN ring hops, etc, etc. The worst-case timeout would
have to factor in all of these variables plus the HN-F cycles for
every line in the L3, and assuming all lines are dirty
In case if L3 is not flushed properly, system behaviour will be
erratic, so remove timeout and add loop to check status of L3 cache.
System will stuck in while loop if there is some issue in L3 cache
flushing.
Signed-off-by: Udit Kumar <udit.kumar@nxp.com>
Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
2019-05-28 16:07:58 +00:00
|
|
|
|
|
|
|
|
mov x0, #0
|
2015-01-06 21:18:42 +00:00
|
|
|
mov lr, x29
|
|
|
|
|
ret
|
2016-10-19 21:18:46 +00:00
|
|
|
ENDPROC(__asm_flush_l3_dcache)
|
2017-08-18 05:24:36 +00:00
|
|
|
#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
|
