2016-09-26 15:09:27 +00:00
|
|
|
config ARCH_LS1021A
|
2016-10-04 21:31:47 +00:00
|
|
|
bool
|
2016-09-26 15:09:27 +00:00
|
|
|
select SYS_FSL_ERRATUM_A010315
|
2016-09-26 15:09:29 +00:00
|
|
|
|
2016-10-04 21:31:48 +00:00
|
|
|
menu "LS102xA architecture"
|
|
|
|
|
depends on ARCH_LS1021A
|
|
|
|
|
|
2016-09-26 15:09:29 +00:00
|
|
|
config LS1_DEEP_SLEEP
|
2016-10-04 21:31:47 +00:00
|
|
|
bool "Deep sleep"
|
|
|
|
|
depends on ARCH_LS1021A
|
2016-10-04 21:31:48 +00:00
|
|
|
|
2016-10-04 21:45:01 +00:00
|
|
|
config MAX_CPUS
|
|
|
|
|
int "Maximum number of CPUs permitted for LS102xA"
|
|
|
|
|
depends on ARCH_LS1021A
|
|
|
|
|
default 2
|
|
|
|
|
help
|
|
|
|
|
Set this number to the maximum number of possible CPUs in the SoC.
|
|
|
|
|
SoCs may have multiple clusters with each cluster may have multiple
|
|
|
|
|
ports. If some ports are reserved but higher ports are used for
|
|
|
|
|
cores, count the reserved ports. This will allocate enough memory
|
|
|
|
|
in spin table to properly handle all cores.
|
|
|
|
|
|
2016-10-04 21:31:48 +00:00
|
|
|
config SYS_FSL_ERRATUM_A010315
|
|
|
|
|
bool "Workaround for PCIe erratum A010315"
|
|
|
|
|
|
|
|
|
|
endmenu
|
