2016-09-26 15:09:27 +00:00
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config ARCH_LS1021A
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2016-10-04 21:31:47 +00:00
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bool
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2016-09-26 15:09:27 +00:00
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select SYS_FSL_ERRATUM_A010315
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2016-09-26 15:09:29 +00:00
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2016-10-04 21:31:48 +00:00
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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2016-09-26 15:09:29 +00:00
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config LS1_DEEP_SLEEP
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2016-10-04 21:31:47 +00:00
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bool "Deep sleep"
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depends on ARCH_LS1021A
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2016-10-04 21:31:48 +00:00
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2016-10-04 21:45:01 +00:00
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config MAX_CPUS
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int "Maximum number of CPUs permitted for LS102xA"
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depends on ARCH_LS1021A
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default 2
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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2016-10-04 21:31:48 +00:00
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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2016-10-04 21:45:54 +00:00
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1021A
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default 8
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2016-10-04 21:31:48 +00:00
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endmenu
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