2008-06-11 12:05:00 +00:00
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/*
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2016-05-04 08:47:31 +00:00
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* sh_eth.c - Driver for Renesas ethernet controller.
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2008-06-11 12:05:00 +00:00
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*
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2011-11-14 07:56:59 +00:00
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* Copyright (C) 2008, 2011 Renesas Solutions Corp.
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2014-11-04 00:15:48 +00:00
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* Copyright (c) 2008, 2011, 2014 2014 Nobuhiro Iwamatsu
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2008-06-11 12:05:00 +00:00
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* Copyright (c) 2007 Carlos Munoz <carlos@kenati.com>
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2014-11-04 00:15:48 +00:00
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* Copyright (C) 2013, 2014 Renesas Electronics Corporation
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2008-06-11 12:05:00 +00:00
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*
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2013-07-08 07:37:19 +00:00
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* SPDX-License-Identifier: GPL-2.0+
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2008-06-11 12:05:00 +00:00
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*/
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#include <config.h>
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#include <common.h>
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2018-04-01 09:22:38 +00:00
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#include <environment.h>
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2008-06-11 12:05:00 +00:00
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#include <malloc.h>
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#include <net.h>
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2008-11-21 03:04:18 +00:00
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#include <netdev.h>
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2011-10-11 09:10:14 +00:00
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#include <miiphy.h>
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2016-09-21 02:28:55 +00:00
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#include <linux/errno.h>
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2008-06-11 12:05:00 +00:00
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#include <asm/io.h>
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2018-01-19 17:57:17 +00:00
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#ifdef CONFIG_DM_ETH
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#include <clk.h>
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#include <dm.h>
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#include <linux/mii.h>
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#include <asm/gpio.h>
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#endif
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2008-06-11 12:05:00 +00:00
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#include "sh_eth.h"
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#ifndef CONFIG_SH_ETHER_USE_PORT
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# error "Please define CONFIG_SH_ETHER_USE_PORT"
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#endif
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#ifndef CONFIG_SH_ETHER_PHY_ADDR
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# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
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#endif
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2013-08-22 04:22:01 +00:00
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2013-08-22 04:22:03 +00:00
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#if defined(CONFIG_SH_ETHER_CACHE_WRITEBACK) && !defined(CONFIG_SYS_DCACHE_OFF)
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#define flush_cache_wback(addr, len) \
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2017-12-01 04:56:08 +00:00
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flush_dcache_range((u32)addr, \
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(u32)(addr + ALIGN(len, CONFIG_SH_ETHER_ALIGNE_SIZE)))
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2011-01-27 01:06:08 +00:00
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#else
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#define flush_cache_wback(...)
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#endif
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2008-06-11 12:05:00 +00:00
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2013-08-22 04:22:03 +00:00
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#if defined(CONFIG_SH_ETHER_CACHE_INVALIDATE) && defined(CONFIG_ARM)
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#define invalidate_cache(addr, len) \
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{ \
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u32 line_size = CONFIG_SH_ETHER_ALIGNE_SIZE; \
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u32 start, end; \
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\
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start = (u32)addr; \
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end = start + len; \
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start &= ~(line_size - 1); \
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end = ((end + line_size - 1) & ~(line_size - 1)); \
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\
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invalidate_dcache_range(start, end); \
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}
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#else
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#define invalidate_cache(...)
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#endif
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2012-01-11 01:23:51 +00:00
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#define TIMEOUT_CNT 1000
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2018-01-21 13:27:51 +00:00
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static int sh_eth_send_common(struct sh_eth_dev *eth, void *packet, int len)
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2008-06-11 12:05:00 +00:00
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{
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2018-02-16 23:46:26 +00:00
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int ret = 0, timeout;
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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2008-06-11 12:05:00 +00:00
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if (!packet || len > 0xffff) {
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2008-11-21 03:04:18 +00:00
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printf(SHETHER_NAME ": %s: Invalid argument\n", __func__);
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ret = -EINVAL;
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goto err;
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2008-06-11 12:05:00 +00:00
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}
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/* packet must be a 4 byte boundary */
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2012-02-02 21:28:49 +00:00
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if ((int)packet & 3) {
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2017-11-30 23:08:00 +00:00
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printf(SHETHER_NAME ": %s: packet not 4 byte aligned\n"
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2014-01-22 22:52:19 +00:00
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, __func__);
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2008-11-21 03:04:18 +00:00
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ret = -EFAULT;
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goto err;
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2008-06-11 12:05:00 +00:00
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}
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/* Update tx descriptor */
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2011-01-27 01:06:08 +00:00
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flush_cache_wback(packet, len);
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2008-06-11 12:05:00 +00:00
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port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
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port_info->tx_desc_cur->td1 = len << 16;
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/* Must preserve the end of descriptor list indication */
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if (port_info->tx_desc_cur->td0 & TD_TDLE)
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP | TD_TDLE;
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else
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port_info->tx_desc_cur->td0 = TD_TACT | TD_TFP;
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2014-11-04 00:15:48 +00:00
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flush_cache_wback(port_info->tx_desc_cur, sizeof(struct tx_desc_s));
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2008-06-11 12:05:00 +00:00
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/* Restart the transmitter if disabled */
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2017-11-30 23:10:32 +00:00
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if (!(sh_eth_read(port_info, EDTRR) & EDTRR_TRNS))
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sh_eth_write(port_info, EDTRR_TRNS, EDTRR);
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2008-06-11 12:05:00 +00:00
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/* Wait until packet is transmitted */
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2012-01-11 01:23:51 +00:00
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timeout = TIMEOUT_CNT;
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2013-08-22 04:22:03 +00:00
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do {
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invalidate_cache(port_info->tx_desc_cur,
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sizeof(struct tx_desc_s));
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2008-06-11 12:05:00 +00:00
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udelay(100);
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2013-08-22 04:22:03 +00:00
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} while (port_info->tx_desc_cur->td0 & TD_TACT && timeout--);
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2008-06-11 12:05:00 +00:00
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if (timeout < 0) {
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2008-11-21 03:04:18 +00:00
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printf(SHETHER_NAME ": transmit timeout\n");
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ret = -ETIMEDOUT;
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2008-06-11 12:05:00 +00:00
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goto err;
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}
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port_info->tx_desc_cur++;
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if (port_info->tx_desc_cur >= port_info->tx_desc_base + NUM_TX_DESC)
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port_info->tx_desc_cur = port_info->tx_desc_base;
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2008-11-21 03:04:18 +00:00
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err:
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return ret;
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2008-06-11 12:05:00 +00:00
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}
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2018-01-21 14:39:50 +00:00
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static int sh_eth_recv_start(struct sh_eth_dev *eth)
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2018-01-21 13:27:51 +00:00
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{
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2018-02-16 23:46:26 +00:00
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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2008-06-11 12:05:00 +00:00
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/* Check if the rx descriptor is ready */
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2013-08-22 04:22:03 +00:00
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invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s));
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2018-01-21 14:39:50 +00:00
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if (port_info->rx_desc_cur->rd0 & RD_RACT)
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return -EINVAL;
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/* Check for errors */
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if (port_info->rx_desc_cur->rd0 & RD_RFE)
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return -EINVAL;
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2018-02-16 23:47:38 +00:00
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return port_info->rx_desc_cur->rd1 & 0xffff;
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2018-01-21 14:39:50 +00:00
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}
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static void sh_eth_recv_finish(struct sh_eth_dev *eth)
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{
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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/* Make current descriptor available again */
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if (port_info->rx_desc_cur->rd0 & RD_RDLE)
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port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
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else
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port_info->rx_desc_cur->rd0 = RD_RACT;
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flush_cache_wback(port_info->rx_desc_cur,
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sizeof(struct rx_desc_s));
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/* Point to the next descriptor */
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port_info->rx_desc_cur++;
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if (port_info->rx_desc_cur >=
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port_info->rx_desc_base + NUM_RX_DESC)
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port_info->rx_desc_cur = port_info->rx_desc_base;
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}
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2008-11-21 03:04:18 +00:00
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static int sh_eth_reset(struct sh_eth_dev *eth)
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2008-06-11 12:05:00 +00:00
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{
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2017-11-30 23:10:32 +00:00
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struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2014-01-22 22:52:18 +00:00
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#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
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2008-11-21 03:04:18 +00:00
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int ret = 0, i;
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2008-06-11 12:05:00 +00:00
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/* Start e-dmac transmitter and receiver */
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2017-11-30 23:10:32 +00:00
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sh_eth_write(port_info, EDSR_ENALL, EDSR);
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2008-06-11 12:05:00 +00:00
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/* Perform a software reset and wait for it to complete */
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2017-11-30 23:10:32 +00:00
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sh_eth_write(port_info, EDMR_SRST, EDMR);
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2014-01-22 22:52:19 +00:00
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for (i = 0; i < TIMEOUT_CNT; i++) {
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2017-11-30 23:10:32 +00:00
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if (!(sh_eth_read(port_info, EDMR) & EDMR_SRST))
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2008-06-11 12:05:00 +00:00
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break;
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udelay(1000);
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}
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|
2012-01-11 01:23:51 +00:00
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if (i == TIMEOUT_CNT) {
|
2008-11-21 03:04:18 +00:00
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printf(SHETHER_NAME ": Software reset timeout\n");
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ret = -EIO;
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2008-06-11 12:05:00 +00:00
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}
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2008-11-21 03:04:18 +00:00
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return ret;
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2011-01-18 08:53:45 +00:00
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#else
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2017-11-30 23:10:32 +00:00
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sh_eth_write(port_info, sh_eth_read(port_info, EDMR) | EDMR_SRST, EDMR);
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2018-02-16 23:57:49 +00:00
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mdelay(3);
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2017-11-30 23:10:32 +00:00
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sh_eth_write(port_info,
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sh_eth_read(port_info, EDMR) & ~EDMR_SRST, EDMR);
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2011-01-18 08:53:45 +00:00
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return 0;
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#endif
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2008-06-11 12:05:00 +00:00
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}
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2008-11-21 03:04:18 +00:00
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static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
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2008-06-11 12:05:00 +00:00
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{
|
2018-02-16 23:46:26 +00:00
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int i, ret = 0;
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2014-11-04 00:15:47 +00:00
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u32 alloc_desc_size = NUM_TX_DESC * sizeof(struct tx_desc_s);
|
2018-02-16 23:46:26 +00:00
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struct sh_eth_info *port_info = ð->port_info[eth->port];
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2008-06-11 12:05:00 +00:00
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struct tx_desc_s *cur_tx_desc;
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|
2008-11-21 03:04:18 +00:00
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/*
|
2014-11-04 00:15:46 +00:00
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* Allocate rx descriptors. They must be aligned to size of struct
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* tx_desc_s.
|
2008-11-21 03:04:18 +00:00
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*/
|
2014-11-04 00:15:47 +00:00
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port_info->tx_desc_alloc =
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memalign(sizeof(struct tx_desc_s), alloc_desc_size);
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|
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if (!port_info->tx_desc_alloc) {
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printf(SHETHER_NAME ": memalign failed\n");
|
2008-11-21 03:04:18 +00:00
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ret = -ENOMEM;
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goto err;
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2008-06-11 12:05:00 +00:00
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}
|
2008-11-21 03:04:18 +00:00
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2017-12-01 04:56:08 +00:00
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flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
|
2014-11-04 00:15:47 +00:00
|
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|
2008-06-11 12:05:00 +00:00
|
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/* Make sure we use a P2 address (non-cacheable) */
|
2014-11-04 00:15:47 +00:00
|
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port_info->tx_desc_base =
|
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(struct tx_desc_s *)ADDR_TO_P2((u32)port_info->tx_desc_alloc);
|
2008-06-11 12:05:00 +00:00
|
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port_info->tx_desc_cur = port_info->tx_desc_base;
|
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|
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/* Initialize all descriptors */
|
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for (cur_tx_desc = port_info->tx_desc_base, i = 0; i < NUM_TX_DESC;
|
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cur_tx_desc++, i++) {
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cur_tx_desc->td0 = 0x00;
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|
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cur_tx_desc->td1 = 0x00;
|
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cur_tx_desc->td2 = 0x00;
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}
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|
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|
/* Mark the end of the descriptors */
|
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cur_tx_desc--;
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cur_tx_desc->td0 |= TD_TDLE;
|
|
|
|
|
2017-11-30 23:08:00 +00:00
|
|
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/*
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|
|
|
* Point the controller to the tx descriptor list. Must use physical
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* addresses
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*/
|
2017-11-30 23:10:32 +00:00
|
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sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
|
2014-01-22 22:52:18 +00:00
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
|
|
|
|
sh_eth_write(port_info, ADDR_TO_PHY(cur_tx_desc), TDFXR);
|
|
|
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sh_eth_write(port_info, 0x01, TDFFR);/* Last discriptor bit */
|
2011-01-18 08:53:45 +00:00
|
|
|
#endif
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
err:
|
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
|
2008-06-11 12:05:00 +00:00
|
|
|
{
|
2018-02-16 23:46:26 +00:00
|
|
|
int i, ret = 0;
|
2014-11-04 00:15:47 +00:00
|
|
|
u32 alloc_desc_size = NUM_RX_DESC * sizeof(struct rx_desc_s);
|
2018-02-16 23:46:26 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2008-06-11 12:05:00 +00:00
|
|
|
struct rx_desc_s *cur_rx_desc;
|
|
|
|
u8 *rx_buf;
|
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
/*
|
2014-11-04 00:15:46 +00:00
|
|
|
* Allocate rx descriptors. They must be aligned to size of struct
|
|
|
|
* rx_desc_s.
|
2008-11-21 03:04:18 +00:00
|
|
|
*/
|
2014-11-04 00:15:47 +00:00
|
|
|
port_info->rx_desc_alloc =
|
|
|
|
memalign(sizeof(struct rx_desc_s), alloc_desc_size);
|
|
|
|
if (!port_info->rx_desc_alloc) {
|
|
|
|
printf(SHETHER_NAME ": memalign failed\n");
|
2008-11-21 03:04:18 +00:00
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
2008-11-21 03:04:18 +00:00
|
|
|
|
2014-11-04 00:15:47 +00:00
|
|
|
flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
|
|
|
|
|
2008-06-11 12:05:00 +00:00
|
|
|
/* Make sure we use a P2 address (non-cacheable) */
|
2014-11-04 00:15:47 +00:00
|
|
|
port_info->rx_desc_base =
|
|
|
|
(struct rx_desc_s *)ADDR_TO_P2((u32)port_info->rx_desc_alloc);
|
2008-06-11 12:05:00 +00:00
|
|
|
|
|
|
|
port_info->rx_desc_cur = port_info->rx_desc_base;
|
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
/*
|
2014-11-04 00:15:47 +00:00
|
|
|
* Allocate rx data buffers. They must be RX_BUF_ALIGNE_SIZE bytes
|
|
|
|
* aligned and in P2 area.
|
2008-11-21 03:04:18 +00:00
|
|
|
*/
|
2014-11-04 00:15:47 +00:00
|
|
|
port_info->rx_buf_alloc =
|
|
|
|
memalign(RX_BUF_ALIGNE_SIZE, NUM_RX_DESC * MAX_BUF_SIZE);
|
|
|
|
if (!port_info->rx_buf_alloc) {
|
|
|
|
printf(SHETHER_NAME ": alloc failed\n");
|
2008-11-21 03:04:18 +00:00
|
|
|
ret = -ENOMEM;
|
2014-11-04 00:15:47 +00:00
|
|
|
goto err_buf_alloc;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
2008-11-21 03:04:18 +00:00
|
|
|
|
2014-11-04 00:15:47 +00:00
|
|
|
port_info->rx_buf_base = (u8 *)ADDR_TO_P2((u32)port_info->rx_buf_alloc);
|
2008-06-11 12:05:00 +00:00
|
|
|
|
|
|
|
/* Initialize all descriptors */
|
|
|
|
for (cur_rx_desc = port_info->rx_desc_base,
|
|
|
|
rx_buf = port_info->rx_buf_base, i = 0;
|
|
|
|
i < NUM_RX_DESC; cur_rx_desc++, rx_buf += MAX_BUF_SIZE, i++) {
|
|
|
|
cur_rx_desc->rd0 = RD_RACT;
|
|
|
|
cur_rx_desc->rd1 = MAX_BUF_SIZE << 16;
|
2017-11-30 23:08:00 +00:00
|
|
|
cur_rx_desc->rd2 = (u32)ADDR_TO_PHY(rx_buf);
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Mark the end of the descriptors */
|
|
|
|
cur_rx_desc--;
|
|
|
|
cur_rx_desc->rd0 |= RD_RDLE;
|
|
|
|
|
|
|
|
/* Point the controller to the rx descriptor list */
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
|
2014-01-22 22:52:18 +00:00
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
|
|
|
|
sh_eth_write(port_info, ADDR_TO_PHY(cur_rx_desc), RDFXR);
|
|
|
|
sh_eth_write(port_info, RDFFR_RDLF, RDFFR);
|
2011-01-18 08:53:45 +00:00
|
|
|
#endif
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
return ret;
|
|
|
|
|
2014-11-04 00:15:47 +00:00
|
|
|
err_buf_alloc:
|
|
|
|
free(port_info->rx_desc_alloc);
|
|
|
|
port_info->rx_desc_alloc = NULL;
|
2008-11-21 03:04:18 +00:00
|
|
|
|
|
|
|
err:
|
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
static void sh_eth_tx_desc_free(struct sh_eth_dev *eth)
|
2008-06-11 12:05:00 +00:00
|
|
|
{
|
2018-02-16 23:46:26 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2014-11-04 00:15:47 +00:00
|
|
|
if (port_info->tx_desc_alloc) {
|
|
|
|
free(port_info->tx_desc_alloc);
|
|
|
|
port_info->tx_desc_alloc = NULL;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
2008-11-21 03:04:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_eth_rx_desc_free(struct sh_eth_dev *eth)
|
|
|
|
{
|
2018-02-16 23:46:26 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2014-11-04 00:15:47 +00:00
|
|
|
if (port_info->rx_desc_alloc) {
|
|
|
|
free(port_info->rx_desc_alloc);
|
|
|
|
port_info->rx_desc_alloc = NULL;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
|
2014-11-04 00:15:47 +00:00
|
|
|
if (port_info->rx_buf_alloc) {
|
|
|
|
free(port_info->rx_buf_alloc);
|
|
|
|
port_info->rx_buf_alloc = NULL;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
static int sh_eth_desc_init(struct sh_eth_dev *eth)
|
2008-06-11 12:05:00 +00:00
|
|
|
{
|
2008-11-21 03:04:18 +00:00
|
|
|
int ret = 0;
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
ret = sh_eth_tx_desc_init(eth);
|
|
|
|
if (ret)
|
|
|
|
goto err_tx_init;
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
ret = sh_eth_rx_desc_init(eth);
|
|
|
|
if (ret)
|
|
|
|
goto err_rx_init;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
err_rx_init:
|
|
|
|
sh_eth_tx_desc_free(eth);
|
|
|
|
|
|
|
|
err_tx_init:
|
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
|
2018-01-21 13:55:44 +00:00
|
|
|
static void sh_eth_write_hwaddr(struct sh_eth_info *port_info,
|
|
|
|
unsigned char *mac)
|
|
|
|
{
|
|
|
|
u32 val;
|
|
|
|
|
|
|
|
val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
|
|
|
|
sh_eth_write(port_info, val, MAHR);
|
|
|
|
|
|
|
|
val = (mac[4] << 8) | mac[5];
|
|
|
|
sh_eth_write(port_info, val, MALR);
|
|
|
|
}
|
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
static void sh_eth_mac_regs_config(struct sh_eth_dev *eth, unsigned char *mac)
|
2008-06-11 12:05:00 +00:00
|
|
|
{
|
2018-01-21 14:10:21 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2008-06-11 12:05:00 +00:00
|
|
|
|
|
|
|
/* Configure e-dmac registers */
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, (sh_eth_read(port_info, EDMR) & ~EMDR_DESC_R) |
|
2013-08-22 04:22:02 +00:00
|
|
|
(EMDR_DESC | EDMR_EL), EDMR);
|
|
|
|
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, 0, EESIPR);
|
|
|
|
sh_eth_write(port_info, 0, TRSCER);
|
|
|
|
sh_eth_write(port_info, 0, TFTR);
|
|
|
|
sh_eth_write(port_info, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
|
|
|
|
sh_eth_write(port_info, RMCR_RST, RMCR);
|
2014-01-22 22:52:18 +00:00
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, 0, RPADIR);
|
2011-01-18 08:53:45 +00:00
|
|
|
#endif
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
|
2008-06-11 12:05:00 +00:00
|
|
|
|
|
|
|
/* Configure e-mac registers */
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, 0, ECSIPR);
|
2008-06-11 12:05:00 +00:00
|
|
|
|
|
|
|
/* Set Mac address */
|
2018-01-21 14:10:21 +00:00
|
|
|
sh_eth_write_hwaddr(port_info, mac);
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, RFLR_RFL_MIN, RFLR);
|
2012-06-26 16:38:06 +00:00
|
|
|
#if defined(SH_ETH_TYPE_GETHER)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, 0, PIPR);
|
2014-01-22 22:52:18 +00:00
|
|
|
#endif
|
|
|
|
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, APR_AP, APR);
|
|
|
|
sh_eth_write(port_info, MPR_MP, MPR);
|
|
|
|
sh_eth_write(port_info, TPAUSER_TPAUSE, TPAUSER);
|
2011-01-18 08:53:45 +00:00
|
|
|
#endif
|
2011-11-14 07:56:59 +00:00
|
|
|
|
2012-08-02 22:08:40 +00:00
|
|
|
#if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, CONFIG_SH_ETHER_SH7734_MII, RMII_MII);
|
2018-01-22 00:42:32 +00:00
|
|
|
#elif defined(CONFIG_RCAR_GEN2)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, sh_eth_read(port_info, RMIIMR) | 0x1, RMIIMR);
|
2012-05-15 15:49:39 +00:00
|
|
|
#endif
|
2018-01-21 14:10:21 +00:00
|
|
|
}
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
static int sh_eth_phy_regs_config(struct sh_eth_dev *eth)
|
|
|
|
{
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
struct phy_device *phy = port_info->phydev;
|
|
|
|
int ret = 0;
|
|
|
|
u32 val = 0;
|
2011-11-14 07:56:59 +00:00
|
|
|
|
2008-06-11 12:05:00 +00:00
|
|
|
/* Set the transfer speed */
|
2011-10-11 09:10:14 +00:00
|
|
|
if (phy->speed == 100) {
|
2008-11-21 03:04:18 +00:00
|
|
|
printf(SHETHER_NAME ": 100Base/");
|
2012-06-26 16:38:06 +00:00
|
|
|
#if defined(SH_ETH_TYPE_GETHER)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, GECMR_100B, GECMR);
|
2012-11-04 15:54:30 +00:00
|
|
|
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, 1, RTRATE);
|
2018-01-22 00:42:32 +00:00
|
|
|
#elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_RCAR_GEN2)
|
2011-11-14 07:56:59 +00:00
|
|
|
val = ECMR_RTM;
|
|
|
|
#endif
|
2011-10-11 09:10:14 +00:00
|
|
|
} else if (phy->speed == 10) {
|
2008-11-21 03:04:18 +00:00
|
|
|
printf(SHETHER_NAME ": 10Base/");
|
2012-06-26 16:38:06 +00:00
|
|
|
#if defined(SH_ETH_TYPE_GETHER)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, GECMR_10B, GECMR);
|
2012-11-04 15:54:30 +00:00
|
|
|
#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, 0, RTRATE);
|
2011-01-18 08:53:45 +00:00
|
|
|
#endif
|
2011-11-14 07:56:59 +00:00
|
|
|
}
|
2012-06-26 16:38:06 +00:00
|
|
|
#if defined(SH_ETH_TYPE_GETHER)
|
2012-05-15 15:49:39 +00:00
|
|
|
else if (phy->speed == 1000) {
|
|
|
|
printf(SHETHER_NAME ": 1000Base/");
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, GECMR_1000B, GECMR);
|
2012-05-15 15:49:39 +00:00
|
|
|
}
|
|
|
|
#endif
|
2008-06-11 12:05:00 +00:00
|
|
|
|
|
|
|
/* Check if full duplex mode is supported by the phy */
|
2011-10-11 09:10:14 +00:00
|
|
|
if (phy->duplex) {
|
2008-06-11 12:05:00 +00:00
|
|
|
printf("Full\n");
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info,
|
2017-11-30 23:08:00 +00:00
|
|
|
val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE | ECMR_DM),
|
2012-06-26 16:38:09 +00:00
|
|
|
ECMR);
|
2008-06-11 12:05:00 +00:00
|
|
|
} else {
|
|
|
|
printf("Half\n");
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info,
|
2017-11-30 23:08:00 +00:00
|
|
|
val | (ECMR_CHG_DM | ECMR_RE | ECMR_TE),
|
|
|
|
ECMR);
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
2008-11-21 03:04:18 +00:00
|
|
|
|
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
static void sh_eth_start(struct sh_eth_dev *eth)
|
2008-06-11 12:05:00 +00:00
|
|
|
{
|
2017-11-30 23:10:32 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
|
2008-06-11 12:05:00 +00:00
|
|
|
/*
|
|
|
|
* Enable the e-dmac receiver only. The transmitter will be enabled when
|
|
|
|
* we have something to transmit
|
|
|
|
*/
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
2008-11-21 03:04:18 +00:00
|
|
|
}
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
static void sh_eth_stop(struct sh_eth_dev *eth)
|
|
|
|
{
|
2017-11-30 23:10:32 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
|
|
|
|
sh_eth_write(port_info, ~EDRRR_R, EDRRR);
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
static int sh_eth_init_common(struct sh_eth_dev *eth, unsigned char *mac)
|
2008-06-11 12:05:00 +00:00
|
|
|
{
|
2008-11-21 03:04:18 +00:00
|
|
|
int ret = 0;
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
ret = sh_eth_reset(eth);
|
|
|
|
if (ret)
|
2018-01-21 14:10:21 +00:00
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
ret = sh_eth_desc_init(eth);
|
|
|
|
if (ret)
|
2018-01-21 14:10:21 +00:00
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
sh_eth_mac_regs_config(eth, mac);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_start_common(struct sh_eth_dev *eth)
|
|
|
|
{
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = phy_startup(port_info->phydev);
|
|
|
|
if (ret) {
|
|
|
|
printf(SHETHER_NAME ": phy startup failure\n");
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sh_eth_phy_regs_config(eth);
|
2008-11-21 03:04:18 +00:00
|
|
|
if (ret)
|
2018-01-21 14:10:21 +00:00
|
|
|
return ret;
|
2008-11-21 03:04:18 +00:00
|
|
|
|
|
|
|
sh_eth_start(eth);
|
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2018-01-19 17:57:17 +00:00
|
|
|
#ifndef CONFIG_DM_ETH
|
2018-01-21 14:31:48 +00:00
|
|
|
static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
|
|
|
|
{
|
2018-02-16 23:46:26 +00:00
|
|
|
int ret = 0;
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2018-01-21 14:31:48 +00:00
|
|
|
struct eth_device *dev = port_info->dev;
|
|
|
|
struct phy_device *phydev;
|
|
|
|
|
|
|
|
phydev = phy_connect(
|
|
|
|
miiphy_get_dev_by_name(dev->name),
|
|
|
|
port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
|
|
|
|
port_info->phydev = phydev;
|
|
|
|
phy_config(phydev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = dev->priv;
|
|
|
|
|
|
|
|
return sh_eth_send_common(eth, packet, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_recv_common(struct sh_eth_dev *eth)
|
|
|
|
{
|
2018-02-16 23:46:26 +00:00
|
|
|
int len = 0;
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2018-01-21 14:31:48 +00:00
|
|
|
uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
|
|
|
|
|
|
|
|
len = sh_eth_recv_start(eth);
|
|
|
|
if (len > 0) {
|
|
|
|
invalidate_cache(packet, len);
|
|
|
|
net_process_received_packet(packet, len);
|
|
|
|
sh_eth_recv_finish(eth);
|
|
|
|
} else
|
|
|
|
len = 0;
|
|
|
|
|
|
|
|
/* Restart the receiver if disabled */
|
|
|
|
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
|
|
|
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
|
|
|
|
|
|
|
return len;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_recv_legacy(struct eth_device *dev)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = dev->priv;
|
|
|
|
|
|
|
|
return sh_eth_recv_common(eth);
|
|
|
|
}
|
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
static int sh_eth_init_legacy(struct eth_device *dev, bd_t *bd)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = dev->priv;
|
|
|
|
int ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
ret = sh_eth_init_common(eth, dev->enetaddr);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = sh_eth_phy_config_legacy(eth);
|
|
|
|
if (ret) {
|
|
|
|
printf(SHETHER_NAME ": phy config timeout\n");
|
|
|
|
goto err_start;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sh_eth_start_common(eth);
|
|
|
|
if (ret)
|
|
|
|
goto err_start;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_start:
|
2008-11-21 03:04:18 +00:00
|
|
|
sh_eth_tx_desc_free(eth);
|
|
|
|
sh_eth_rx_desc_free(eth);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2018-01-21 14:10:21 +00:00
|
|
|
void sh_eth_halt_legacy(struct eth_device *dev)
|
2008-11-21 03:04:18 +00:00
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = dev->priv;
|
2017-11-30 23:08:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
sh_eth_stop(eth);
|
|
|
|
}
|
|
|
|
|
|
|
|
int sh_eth_initialize(bd_t *bd)
|
|
|
|
{
|
2014-01-22 22:52:19 +00:00
|
|
|
int ret = 0;
|
2008-11-21 03:04:18 +00:00
|
|
|
struct sh_eth_dev *eth = NULL;
|
2014-01-22 22:52:19 +00:00
|
|
|
struct eth_device *dev = NULL;
|
2017-11-30 23:08:00 +00:00
|
|
|
struct mii_dev *mdiodev;
|
2008-11-21 03:04:18 +00:00
|
|
|
|
2014-01-22 22:52:19 +00:00
|
|
|
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
|
2008-11-21 03:04:18 +00:00
|
|
|
if (!eth) {
|
|
|
|
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
|
|
|
|
ret = -ENOMEM;
|
2008-06-11 12:05:00 +00:00
|
|
|
goto err;
|
2008-11-21 03:04:18 +00:00
|
|
|
}
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2014-01-22 22:52:19 +00:00
|
|
|
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
|
2008-11-21 03:04:18 +00:00
|
|
|
if (!dev) {
|
|
|
|
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
|
|
|
|
ret = -ENOMEM;
|
|
|
|
goto err;
|
|
|
|
}
|
2014-01-22 22:52:19 +00:00
|
|
|
memset(dev, 0, sizeof(struct eth_device));
|
|
|
|
memset(eth, 0, sizeof(struct sh_eth_dev));
|
2008-06-11 12:05:00 +00:00
|
|
|
|
2008-11-21 03:04:18 +00:00
|
|
|
eth->port = CONFIG_SH_ETHER_USE_PORT;
|
|
|
|
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
|
2017-11-30 23:10:32 +00:00
|
|
|
eth->port_info[eth->port].iobase =
|
|
|
|
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
|
2008-11-21 03:04:18 +00:00
|
|
|
|
2014-01-22 22:52:19 +00:00
|
|
|
dev->priv = (void *)eth;
|
|
|
|
dev->iobase = 0;
|
2018-01-21 14:10:21 +00:00
|
|
|
dev->init = sh_eth_init_legacy;
|
|
|
|
dev->halt = sh_eth_halt_legacy;
|
2018-01-21 13:27:51 +00:00
|
|
|
dev->send = sh_eth_send_legacy;
|
|
|
|
dev->recv = sh_eth_recv_legacy;
|
2014-01-22 22:52:19 +00:00
|
|
|
eth->port_info[eth->port].dev = dev;
|
2008-11-21 03:04:18 +00:00
|
|
|
|
2015-12-30 13:05:58 +00:00
|
|
|
strcpy(dev->name, SHETHER_NAME);
|
2008-11-21 03:04:18 +00:00
|
|
|
|
2014-01-22 22:52:19 +00:00
|
|
|
/* Register Device to EtherNet subsystem */
|
|
|
|
eth_register(dev);
|
2008-11-21 03:04:18 +00:00
|
|
|
|
2011-10-11 09:10:14 +00:00
|
|
|
bb_miiphy_buses[0].priv = eth;
|
2017-11-30 23:08:00 +00:00
|
|
|
mdiodev = mdio_alloc();
|
2016-08-08 16:28:38 +00:00
|
|
|
if (!mdiodev)
|
|
|
|
return -ENOMEM;
|
|
|
|
strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
|
|
|
|
mdiodev->read = bb_miiphy_read;
|
|
|
|
mdiodev->write = bb_miiphy_write;
|
|
|
|
|
2017-11-30 23:08:00 +00:00
|
|
|
ret = mdio_register(mdiodev);
|
|
|
|
if (ret < 0)
|
|
|
|
return ret;
|
2011-10-11 09:10:14 +00:00
|
|
|
|
2017-08-03 18:22:14 +00:00
|
|
|
if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
|
2009-02-12 00:14:09 +00:00
|
|
|
puts("Please set MAC address\n");
|
2008-11-21 03:04:18 +00:00
|
|
|
|
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
|
|
|
|
err:
|
2008-11-21 03:04:18 +00:00
|
|
|
if (dev)
|
|
|
|
free(dev);
|
|
|
|
|
|
|
|
if (eth)
|
|
|
|
free(eth);
|
|
|
|
|
|
|
|
printf(SHETHER_NAME ": Failed\n");
|
|
|
|
return ret;
|
2008-06-11 12:05:00 +00:00
|
|
|
}
|
2011-10-11 09:10:14 +00:00
|
|
|
|
2018-01-19 17:57:17 +00:00
|
|
|
#else /* CONFIG_DM_ETH */
|
|
|
|
|
|
|
|
struct sh_ether_priv {
|
|
|
|
struct sh_eth_dev shdev;
|
|
|
|
|
|
|
|
struct mii_dev *bus;
|
2018-02-16 23:57:49 +00:00
|
|
|
phys_addr_t iobase;
|
2018-01-19 17:57:17 +00:00
|
|
|
struct clk clk;
|
|
|
|
struct gpio_desc reset_gpio;
|
|
|
|
};
|
|
|
|
|
|
|
|
static int sh_ether_send(struct udevice *dev, void *packet, int len)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
|
|
|
|
return sh_eth_send_common(eth, packet, len);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
|
|
|
|
int len;
|
|
|
|
|
|
|
|
len = sh_eth_recv_start(eth);
|
|
|
|
if (len > 0) {
|
|
|
|
invalidate_cache(packet, len);
|
|
|
|
*packetp = packet;
|
|
|
|
|
|
|
|
return len;
|
|
|
|
} else {
|
|
|
|
len = 0;
|
|
|
|
|
|
|
|
/* Restart the receiver if disabled */
|
|
|
|
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
|
|
|
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
|
|
|
|
|
|
|
return -EAGAIN;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
|
|
|
|
sh_eth_recv_finish(eth);
|
|
|
|
|
|
|
|
/* Restart the receiver if disabled */
|
|
|
|
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
|
|
|
|
sh_eth_write(port_info, EDRRR_R, EDRRR);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_ether_write_hwaddr(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
|
|
|
|
sh_eth_write_hwaddr(port_info, pdata->enetaddr);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_phy_config(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
2018-02-16 23:46:26 +00:00
|
|
|
int ret = 0;
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2018-01-19 17:57:17 +00:00
|
|
|
struct phy_device *phydev;
|
|
|
|
int mask = 0xffffffff;
|
|
|
|
|
|
|
|
phydev = phy_find_by_mask(priv->bus, mask, pdata->phy_interface);
|
|
|
|
if (!phydev)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
phy_connect_dev(phydev, dev);
|
|
|
|
|
|
|
|
port_info->phydev = phydev;
|
|
|
|
phy_config(phydev);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_ether_start(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
ret = clk_enable(&priv->clk);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
ret = sh_eth_init_common(eth, pdata->enetaddr);
|
|
|
|
if (ret)
|
|
|
|
goto err_clk;
|
|
|
|
|
|
|
|
ret = sh_eth_phy_config(dev);
|
|
|
|
if (ret) {
|
|
|
|
printf(SHETHER_NAME ": phy config timeout\n");
|
|
|
|
goto err_start;
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = sh_eth_start_common(eth);
|
|
|
|
if (ret)
|
|
|
|
goto err_start;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_start:
|
|
|
|
sh_eth_tx_desc_free(eth);
|
|
|
|
sh_eth_rx_desc_free(eth);
|
|
|
|
err_clk:
|
|
|
|
clk_disable(&priv->clk);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void sh_ether_stop(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(dev);
|
|
|
|
|
|
|
|
sh_eth_stop(&priv->shdev);
|
|
|
|
clk_disable(&priv->clk);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_ether_probe(struct udevice *udev)
|
|
|
|
{
|
|
|
|
struct eth_pdata *pdata = dev_get_platdata(udev);
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(udev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
struct mii_dev *mdiodev;
|
|
|
|
int ret;
|
|
|
|
|
2018-02-16 23:57:49 +00:00
|
|
|
priv->iobase = pdata->iobase;
|
2018-01-19 17:57:17 +00:00
|
|
|
|
|
|
|
ret = clk_get_by_index(udev, 0, &priv->clk);
|
|
|
|
if (ret < 0)
|
2018-02-16 23:57:49 +00:00
|
|
|
return ret;
|
2018-01-19 17:57:17 +00:00
|
|
|
|
|
|
|
gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio,
|
|
|
|
GPIOD_IS_OUT);
|
|
|
|
|
|
|
|
mdiodev = mdio_alloc();
|
|
|
|
if (!mdiodev) {
|
|
|
|
ret = -ENOMEM;
|
2018-02-16 23:57:49 +00:00
|
|
|
return ret;
|
2018-01-19 17:57:17 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
mdiodev->read = bb_miiphy_read;
|
|
|
|
mdiodev->write = bb_miiphy_write;
|
|
|
|
bb_miiphy_buses[0].priv = eth;
|
|
|
|
snprintf(mdiodev->name, sizeof(mdiodev->name), udev->name);
|
|
|
|
|
|
|
|
ret = mdio_register(mdiodev);
|
|
|
|
if (ret < 0)
|
|
|
|
goto err_mdio_register;
|
|
|
|
|
|
|
|
priv->bus = miiphy_get_dev_by_name(udev->name);
|
|
|
|
|
|
|
|
eth->port = CONFIG_SH_ETHER_USE_PORT;
|
|
|
|
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
|
|
|
|
eth->port_info[eth->port].iobase =
|
|
|
|
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err_mdio_register:
|
|
|
|
mdio_free(mdiodev);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_ether_remove(struct udevice *udev)
|
|
|
|
{
|
|
|
|
struct sh_ether_priv *priv = dev_get_priv(udev);
|
|
|
|
struct sh_eth_dev *eth = &priv->shdev;
|
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
|
|
|
|
|
|
|
free(port_info->phydev);
|
|
|
|
mdio_unregister(priv->bus);
|
|
|
|
mdio_free(priv->bus);
|
|
|
|
|
|
|
|
if (dm_gpio_is_valid(&priv->reset_gpio))
|
|
|
|
dm_gpio_free(udev, &priv->reset_gpio);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct eth_ops sh_ether_ops = {
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.start = sh_ether_start,
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.send = sh_ether_send,
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.recv = sh_ether_recv,
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.free_pkt = sh_ether_free_pkt,
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.stop = sh_ether_stop,
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.write_hwaddr = sh_ether_write_hwaddr,
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};
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int sh_ether_ofdata_to_platdata(struct udevice *dev)
|
|
|
|
{
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|
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|
struct eth_pdata *pdata = dev_get_platdata(dev);
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const char *phy_mode;
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const fdt32_t *cell;
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int ret = 0;
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pdata->iobase = devfdt_get_addr(dev);
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pdata->phy_interface = -1;
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phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
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NULL);
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if (phy_mode)
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pdata->phy_interface = phy_get_interface_by_name(phy_mode);
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|
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if (pdata->phy_interface == -1) {
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debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
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return -EINVAL;
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}
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pdata->max_speed = 1000;
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cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
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if (cell)
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pdata->max_speed = fdt32_to_cpu(*cell);
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sprintf(bb_miiphy_buses[0].name, dev->name);
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return ret;
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}
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|
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static const struct udevice_id sh_ether_ids[] = {
|
2018-04-12 13:23:46 +00:00
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{ .compatible = "renesas,ether-r8a7790" },
|
2018-01-19 17:57:17 +00:00
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{ .compatible = "renesas,ether-r8a7791" },
|
2018-04-12 13:23:46 +00:00
|
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{ .compatible = "renesas,ether-r8a7793" },
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{ .compatible = "renesas,ether-r8a7794" },
|
2018-01-19 17:57:17 +00:00
|
|
|
{ }
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|
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};
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|
|
U_BOOT_DRIVER(eth_sh_ether) = {
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.name = "sh_ether",
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|
|
.id = UCLASS_ETH,
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|
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.of_match = sh_ether_ids,
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|
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.ofdata_to_platdata = sh_ether_ofdata_to_platdata,
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|
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.probe = sh_ether_probe,
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|
|
.remove = sh_ether_remove,
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|
|
.ops = &sh_ether_ops,
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|
|
.priv_auto_alloc_size = sizeof(struct sh_ether_priv),
|
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|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
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|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
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|
|
};
|
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|
|
#endif
|
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|
|
2011-10-11 09:10:14 +00:00
|
|
|
/******* for bb_miiphy *******/
|
|
|
|
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = bus->priv;
|
2017-11-30 23:10:32 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2011-10-11 09:10:14 +00:00
|
|
|
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, sh_eth_read(port_info, PIR) | PIR_MMD, PIR);
|
2011-10-11 09:10:14 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = bus->priv;
|
2017-11-30 23:10:32 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2011-10-11 09:10:14 +00:00
|
|
|
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info, sh_eth_read(port_info, PIR) & ~PIR_MMD, PIR);
|
2011-10-11 09:10:14 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = bus->priv;
|
2017-11-30 23:10:32 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2011-10-11 09:10:14 +00:00
|
|
|
|
|
|
|
if (v)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info,
|
|
|
|
sh_eth_read(port_info, PIR) | PIR_MDO, PIR);
|
2011-10-11 09:10:14 +00:00
|
|
|
else
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info,
|
|
|
|
sh_eth_read(port_info, PIR) & ~PIR_MDO, PIR);
|
2011-10-11 09:10:14 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = bus->priv;
|
2017-11-30 23:10:32 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2011-10-11 09:10:14 +00:00
|
|
|
|
2017-11-30 23:10:32 +00:00
|
|
|
*v = (sh_eth_read(port_info, PIR) & PIR_MDI) >> 3;
|
2011-10-11 09:10:14 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
|
|
|
|
{
|
|
|
|
struct sh_eth_dev *eth = bus->priv;
|
2017-11-30 23:10:32 +00:00
|
|
|
struct sh_eth_info *port_info = ð->port_info[eth->port];
|
2011-10-11 09:10:14 +00:00
|
|
|
|
|
|
|
if (v)
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info,
|
|
|
|
sh_eth_read(port_info, PIR) | PIR_MDC, PIR);
|
2011-10-11 09:10:14 +00:00
|
|
|
else
|
2017-11-30 23:10:32 +00:00
|
|
|
sh_eth_write(port_info,
|
|
|
|
sh_eth_read(port_info, PIR) & ~PIR_MDC, PIR);
|
2011-10-11 09:10:14 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int sh_eth_bb_delay(struct bb_miiphy_bus *bus)
|
|
|
|
{
|
|
|
|
udelay(10);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct bb_miiphy_bus bb_miiphy_buses[] = {
|
|
|
|
{
|
|
|
|
.name = "sh_eth",
|
|
|
|
.init = sh_eth_bb_init,
|
|
|
|
.mdio_active = sh_eth_bb_mdio_active,
|
|
|
|
.mdio_tristate = sh_eth_bb_mdio_tristate,
|
|
|
|
.set_mdio = sh_eth_bb_set_mdio,
|
|
|
|
.get_mdio = sh_eth_bb_get_mdio,
|
|
|
|
.set_mdc = sh_eth_bb_set_mdc,
|
|
|
|
.delay = sh_eth_bb_delay,
|
|
|
|
}
|
|
|
|
};
|
2017-11-30 23:08:00 +00:00
|
|
|
|
2011-10-11 09:10:14 +00:00
|
|
|
int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
|