Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-10 15:14:43 +00:00
Code Issues Projects Releases Packages Wiki Activity

net: sh_eth: add cache handling

Browse source 
Some CPU needs cache handling. So this patch add the config of
CONFIG_SH_ETHER_CACHE_WRITEBACK, and it calls wback function.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
This commit is contained in:
Yoshihiro Shimoda 2011-01-27 10:06:08 +09:00 committed by Nobuhiro Iwamatsu
parent 3d0075fa7a
commit 68260aab93
2 changed files with 12 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
README
View file

@ -901,6 +901,9 @@ The following options need to be configured:
CONFIG_SH_ETHER_PHY_ADDR
Define the ETH PHY's address
CONFIG_SH_ETHER_CACHE_WRITEBACK
If this option is set, the driver enables cache flush.
- USB Support:
At the moment only the UHCI host controller is
supported (PIP405, MIP405, MPC5200); define

9
drivers/net/sh_eth.c
View file

@ -36,6 +36,12 @@
#ifndef CONFIG_SH_ETHER_PHY_ADDR
# error "Please define CONFIG_SH_ETHER_PHY_ADDR"
#endif
#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK
#define flush_cache_wback(addr, len) \
dcache_wback_range((u32)addr, (u32)(addr + len - 1))
#else
#define flush_cache_wback(...)
#endif
#define SH_ETH_PHY_DELAY 50000
@ -197,6 +203,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len)
}
/* Update tx descriptor */
flush_cache_wback(packet, len);
port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet);
port_info->tx_desc_cur->td1 = len << 16;
/* Must preserve the end of descriptor list indication */
@ -312,6 +319,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth)
tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) &
~(TX_DESC_SIZE - 1));
flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr);
port_info->tx_desc_cur = port_info->tx_desc_base;
@ -361,6 +369,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth)
tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) &
~(RX_DESC_SIZE - 1));
flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s));
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr);