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22 commits

Author SHA1 Message Date
Asahi Lina
8cd2865c1f m1n1.sysreg & co: Add support for op-like sysregs (e.g. TLBI)
Signed-off-by: Asahi Lina <lina@asahilina.net>
2022-08-17 14:01:07 +09:00
Hector Martin
e00e9574d0 tools/reg_filter.py: Decode trivial values into BIT()
Signed-off-by: Hector Martin <marcan@marcan.st>
2022-06-28 01:41:23 +09:00
Hector Martin
d9c1ef7d49 cpu_regs: Add new defines for T8112 chickens
Signed-off-by: Hector Martin <marcan@marcan.st>
2022-06-28 01:41:23 +09:00
Hector Martin
4652ac2098 tools/reg_filter.py: Tool to add IMPDEF sysreg names to a disasm
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-11-16 17:18:09 +09:00
Hector Martin
6707fd5bb9 tools/gen_reg_class.py: Fix multibit field defs
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-09-21 23:28:42 +09:00
Hector Martin
a3558c86d7 tools/gen_reg_class.py: Script to generate Register classes
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-06-10 19:44:20 +09:00
Janne Grunau
8bf2763e57 apple_regs: annotate perf monitor system register fields
Signed-off-by: Janne Grunau <j@jannau.net>
2021-06-09 19:47:20 +09:00
Hector Martin
f1cfe27e31 hv: Use AFSR_GL1 when in guarded mode.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-30 03:34:17 +09:00
Hector Martin
3b6f32775b apple_regs.json: IPI and VM timer reg bit definitions
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-25 19:50:05 +09:00
Hector Martin
81bf0ad578 apple_regs.json: More GXF and SPRR registers
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-22 04:42:38 +09:00
Hector Martin
aacbdf0949 GXF_STATUS -> GXF_STATUS_EL1
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-22 04:42:38 +09:00
Hector Martin
3bc591708b apple_regs.json: Add GXF_CONFIG_EL{2, 12}
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-22 03:21:01 +09:00
Hector Martin
d82f5db064 apple_regs.json: Add CNTPCT_ALIAS_EL0
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-22 03:21:01 +09:00
Adam Reviczky
570bfa1a17
apple_regs: add missing brackets ()
apple_regs.json: Typo: add some missing brackets.

Signed-off-by: Adam Reviczky <adam.reviczky@kclalumni.net>
2021-05-16 02:42:20 +09:00
Sven Peter
4a893dc57a apple_regs: document more SPRR regs
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-15 16:38:45 +09:00
Sven Peter
d324e368b8 apple_regs.json: fix EL3 typo
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-15 16:38:45 +09:00
Hector Martin
248011f7a1 apple_regs.json: Correct VM pauth registers
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 21:28:31 +09:00
Hector Martin
757213b7a9 apple_regs.json: Add some EL1 registers for AP
Still not sure how to enable APSTS_EL12...

Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-13 20:10:34 +09:00
Hector Martin
857d518950 apple_regs.json: Reformat and add many more registers
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-12 21:20:26 +09:00
Sven Peter
1c604a77c5 gxf: add support for guarded exception levels
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
2c5b202c99 sysreg: add support for Apple's custom sysregs
Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Hector Martin
a489a646bd Add tools for ARM sysreg database management
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-01 15:14:35 +09:00