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apple_regs: add missing brackets (#55)

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apple_regs.json: Typo: add some missing brackets.

Signed-off-by: Adam Reviczky <adam.reviczky@kclalumni.net>
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Adam Reviczky 2021-05-15 18:42:20 +01:00 committed by GitHub
parent 3283987ba9
commit 570bfa1a17
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GPG key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 2 deletions
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tools/apple_regs.json
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@ -66,7 +66,7 @@
{"index": 0, "name": "APRR_EL1", "fullname": "APRR EL1", "enc": [3, 4, 15, 2, 1 ], "width": 64},
{"index": 0, "name": "CTRR_LOCK_EL1", "fullname": "CTRR Lock", "enc": [3, 4, 15, 2, 2 ], "width": 64},
{"index": 0, "name": "CTRR_A_LWR_EL1", "fullname": "CTRR A Lower Address (EL1)", "enc": [3, 4, 15, 2, 3 ], "width": 64},
{"index": 0, "name": "CTRR_A_UPR_EL1", "fullname": "CTRR A Upper Address (EL1", "enc": [3, 4, 15, 2, 4 ], "width": 64},
{"index": 0, "name": "CTRR_A_UPR_EL1", "fullname": "CTRR A Upper Address (EL1)", "enc": [3, 4, 15, 2, 4 ], "width": 64},
{"index": 0, "name": "CTRR_CTL_EL1", "fullname": "CTRR Control (EL1)", "enc": [3, 4, 15, 2, 5 ], "width": 64},
{"index": 0, "name": "APRR_JIT_ENABLE_EL2", "fullname": "APRR JIT Enable", "enc": [3, 4, 15, 2, 6 ], "width": 64},
{"index": 0, "name": "APRR_JIT_MASK_EL2", "fullname": "APRR JIT Mask", "enc": [3, 4, 15, 2, 7 ], "width": 64},
@ -87,7 +87,7 @@
{"index": 0, "name": "CTRR_CTL_EL2", "fullname": "CTRR Control (EL2)", "enc": [3, 4, 15, 11, 4 ], "width": 64},
{"index": 0, "name": "CTRR_LOCK_EL2", "fullname": "CTRR Lock", "enc": [3, 4, 15, 11, 5 ], "width": 64},
{"index": 0, "name": "IPI_RR_LOCAL_EL1", "fullname": "IPI Request Register (Local)", "enc": [3, 5, 15, 0, 0 ], "width": 64},
{"index": 0, "name": "IPI_RR_GLOBAL_EL1", "fullname": "IPI Request Register (Global", "enc": [3, 5, 15, 0, 1 ], "width": 64},
{"index": 0, "name": "IPI_RR_GLOBAL_EL1", "fullname": "IPI Request Register (Global)", "enc": [3, 5, 15, 0, 1 ], "width": 64},
{"index": 0, "name": "DPC_ERR_STS_EL1", "fullname": "DPC Error Status", "enc": [3, 5, 15, 0, 5 ], "width": 64},
{"index": 0, "name": "IPI_SR_EL1", "fullname": "IPI Status Register", "enc": [3, 5, 15, 1, 1 ], "width": 64},
{"index": 0, "name": "VM_TMR_LR_EL2", "fullname": "VM Timer Link Register", "enc": [3, 5, 15, 1, 2 ], "width": 64},