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https://github.com/AsahiLinux/m1n1
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Add tools for ARM sysreg database management
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
parent
7bb490eb58
commit
a489a646bd
6 changed files with 159 additions and 4 deletions
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@ -49,8 +49,6 @@ class ADTNode:
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self.children = []
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self.properties = {}
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if val is not None:
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for p in val.properties:
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if p.name == "name":
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@ -4,7 +4,7 @@ from tgtypes import *
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import malloc
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def load_registers():
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data = json.load(open(os.path.join(os.path.dirname(__file__), "regs.json")))
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data = json.load(open(os.path.join(os.path.dirname(__file__), "..", "tools", "arm_regs.json")))
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for reg in data:
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yield reg["name"], reg["enc"]
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File diff suppressed because one or more lines are too long
1
tools/arm_regs.json
Normal file
1
tools/arm_regs.json
Normal file
File diff suppressed because one or more lines are too long
24
tools/gen_reg_include.py
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24
tools/gen_reg_include.py
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@ -0,0 +1,24 @@
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import json, sys
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data = json.load(open(sys.argv[1]))
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for reg in data:
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name = reg['name']
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print(f"#define SYS_{name} sys_reg({', '.join(str(i) for i in reg['enc'])})")
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if name[-4:-1] == "_EL":
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name = name[:-4]
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for fieldset in reg["fieldsets"]:
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if "instance" in fieldset:
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print(f"// {fieldset['instance']}")
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for f in fieldset["fields"]:
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fname = f["name"]
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msb, lsb = f["msb"], f["lsb"]
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if msb == lsb:
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print(f"#define {name}_{fname} BIT({lsb})")
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else:
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print(f"#define {name}_{fname} GENMASK({msb}, {lsb})")
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print()
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133
tools/reg2json.py
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133
tools/reg2json.py
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@ -0,0 +1,133 @@
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import sys, re, json
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from xml.etree import ElementTree
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def insert_n(s, nb):
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sout = ""
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def sub(g):
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if g.group(2):
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a, b = int(g.group(1)), int(g.group(2)[1:])
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return nb[-a - 1:-b or None]
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else:
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a = int(g.group(1))
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return nb[-a - 1]
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s = re.sub(r'n\[(\d+)(:\d+)?\]', sub, s)
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s = "".join(s.split(":"))
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return int(s.replace("0b", ""), 2)
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def parse_one(regs, xml):
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t = ElementTree.parse(xml)
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for reg in t.findall('registers/register'):
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data = {}
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name = reg.find('reg_short_name').text
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fullname = reg.find('reg_long_name').text
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if name.startswith("S3_"):
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continue
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array = reg.find('reg_array')
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start = end = 0
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if array:
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start = int(array.find("reg_array_start").text)
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end = int(array.find("reg_array_end").text)
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encs = {}
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for am in reg.findall('access_mechanisms/access_mechanism'):
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accessor = am.attrib["accessor"]
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if not accessor.startswith("MSRregister ") and not accessor.startswith("MRS "):
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continue
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regname = accessor.split(" ", 1)[1]
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enc = {}
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for e in am.findall("encoding/enc"):
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enc[e.attrib["n"]] = e.attrib["v"]
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enc = enc["op0"], enc["op1"], enc["CRn"], enc["CRm"], enc["op2"]
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if regname in encs:
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assert encs[regname] == enc
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encs[regname] = enc
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if not encs:
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continue
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fieldsets = []
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width = None
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for fields_elem in reg.findall('reg_fieldsets/fields'):
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fieldset = {}
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if (instance_elem := fields_elem.find('fields_instance')) is not None:
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fieldset["instance"] = instance_elem.text
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fields = []
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set_width = int(fields_elem.attrib["length"])
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if width is None:
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width = set_width
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else:
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assert width == set_width
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single_field = False
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for f in fields_elem.findall('field'):
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if f.attrib.get("rwtype", None) in ("RES0", "RES1", "RAZ", "RAZ/WI", "RAO/WI", "UNKNOWN"):
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continue
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msb, lsb = int(f.find('field_msb').text), int(f.find('field_lsb').text)
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assert not single_field
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if msb == width - 1 and lsb == 0:
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continue
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if (name_elem := f.find('field_name')) is not None:
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name = name_elem.text
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else:
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assert not fields
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continue
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field = {
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"name": name,
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"msb": msb,
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"lsb": lsb,
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}
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fields.append(field)
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fields.sort(key=lambda x: x["lsb"], reverse=True)
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fieldset["fields"] = fields
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fieldsets.append(fieldset)
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for idx, n in enumerate(range(start, end + 1)):
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nb = "{0:064b}".format(n)[::-1]
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for name, enc in sorted(encs.items()):
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enc = tuple(insert_n(i, nb) for i in enc)
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data = {
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"index": idx,
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"name": name.replace("<n>", "%d" % n),
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"fullname": fullname,
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"enc": enc,
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"fieldsets": fieldsets,
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}
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if width is not None:
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data["width"] = width
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yield data
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if __name__ == "__main__":
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regs = []
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for i in sys.argv[1:]:
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regs.extend(parse_one(regs, i))
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json.dump(regs, sys.stdout)
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