Hector Martin
33d09cc7c0
hv_exc: Filter out CYC_OVRD_DISABLE_WFI_RET
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-11-16 17:26:39 +09:00
Hector Martin
b50a489f41
chickens: Update Firestorm chickens & complete t600x
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-11-11 01:20:03 +09:00
Hector Martin
f5af1caee5
hv_exc: Forward more sysregs
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We don't normally trap these, but for experiments using TIDCP they are
useful to avoid.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-11-04 03:55:09 +09:00
Hector Martin
ed21a80bc3
chickens: Refactor and update M1 bits
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This adds some missing fixes for M1/T8103 and reworks the code to split
off common parts, and also handle per-revision bits.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-11-01 13:41:12 +09:00
Hector Martin
2f8beb02b4
cpu_regs.h: Add more registers needed for HV config
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-09-15 23:24:37 +09:00
Janne Grunau
4b5c016368
hv: disable PMU counters inside the hypervisor
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Signed-off-by: Janne Grunau <j@jannau.net>
2021-06-09 19:47:20 +09:00
Janne Grunau
d61bf13cb0
hv: shadow perf monitor IRQ mode and state
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The development Mac OS kernel panics if the PMCR0 sysreg is in an
unexpected state. To avoid that the hypervisor needs to shadow the
interrupt mode and interrupt active flag after it mask the PM FIQ.
Mac OS reads and writes frequently from PMCR0 and PMC 0/1 so handling
in m1n1 is preferred over Python.
Signed-off-by: Janne Grunau <j@jannau.net>
2021-06-09 19:47:20 +09:00
Hector Martin
f1cfe27e31
hv: Use AFSR_GL1 when in guarded mode.
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-30 03:34:17 +09:00
Hector Martin
dd443d2c2c
cpu_regs: Fix missing IMP_APL prefixes
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-28 00:38:11 +09:00
Hector Martin
0265edebba
hv_exc: Add ACTLR_EL1 sysreg forwarding
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-28 00:37:48 +09:00
Hector Martin
48c7fc725b
cpu_regs.h: Add IPI and VM timer reg defines
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-25 20:12:20 +09:00
Hector Martin
e484d6df70
cpu_regs.h: Add Apple-defined exception types
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-25 20:12:20 +09:00
Hector Martin
aacbdf0949
GXF_STATUS -> GXF_STATUS_EL1
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-22 04:42:38 +09:00
Sven Peter
4a893dc57a
apple_regs: document more SPRR regs
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-15 16:38:45 +09:00
Sven Peter
1c604a77c5
gxf: add support for guarded exception levels
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Sven Peter
36efdd2ac3
allow cpu_regs.h to be included in .S files
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Signed-off-by: Sven Peter <sven@svenpeter.dev>
2021-05-11 15:48:40 +09:00
Hector Martin
1ae60ad715
hv: Beginnings of a hypervisor
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-05-01 19:21:33 +09:00
Hector Martin
882610b50e
cpu_regs.h: s/SYS_APL/SYS_IMP_APL/ to match Linux
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-04-29 15:45:44 +09:00
Hector Martin
b5cbf7360e
exception: handle PMC FIQs
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-18 17:55:55 +09:00
Hector Martin
86a7d9c0f3
cpu_regs.h: s/SYS_/SYS_APL_/
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This synchronizes the register naming convention with Linux
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-18 17:55:55 +09:00
Hector Martin
aaab2c6ca1
chickens: set WFI mode to clockgate only
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This preserves CPU registers.
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-02-05 02:58:08 +09:00
Hector Martin
bbe47b2f75
Move Apple ARM register definitions to cpu_regs.h
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Signed-off-by: Hector Martin <marcan@marcan.st>
2021-01-30 22:00:00 +09:00
