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https://github.com/AsahiLinux/m1n1
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chickens: Update Firestorm chickens & complete t600x
Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
efca793572
commit
b50a489f41
2 changed files with 88 additions and 49 deletions
132
src/chickens.c
132
src/chickens.c
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@ -19,21 +19,7 @@
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#define MIDR_PART GENMASK(15, 4)
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#define MIDR_REV_HIGH GENMASK(23, 20)
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void init_common(void)
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{
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int core = mrs(MPIDR_EL1) & 0xff;
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// Unknown, related to SMP?
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msr(s3_4_c15_c5_0, core);
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msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
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// Enable IRQs (at least necessary on t600x)
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msr(s3_4_c15_c10_4, 0);
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sysop("isb");
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}
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void init_common_icestorm(void)
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static void init_common_icestorm(void)
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{
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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@ -48,7 +34,7 @@ void init_common_icestorm(void)
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reg_set(SYS_IMP_APL_EHID20, EHID20_TRAP_SMC);
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}
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void init_common_firestorm(void)
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static void init_common_firestorm(void)
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{
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reg_set(SYS_IMP_APL_HID0, HID0_SAME_PG_POWER_OPTIMIZATION);
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@ -78,10 +64,8 @@ void init_common_firestorm(void)
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HID16_ENABLE_MP_CYCLONE_7);
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}
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void init_m1_icestorm(int rev)
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static void init_m1_icestorm(void)
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{
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UNUSED(rev);
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init_common_icestorm();
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reg_set(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER |
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@ -89,50 +73,85 @@ void init_m1_icestorm(int rev)
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reg_mask(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL_MASK,
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EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL(3));
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init_common();
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}
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void init_m1_firestorm(int rev)
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static void init_m1_firestorm(void)
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{
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if (rev < 0x10)
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printf(" Revisions <0x10 not supported!\n");
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init_common_firestorm();
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// "Cross-beat Crypto(AES/PMUL) ICache fusion is not disabled for branch
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// uncondtional "recoded instruction."
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reg_set(SYS_IMP_APL_HID0, HID0_FETCH_WIDTH_DISABLE | HID0_CACHE_FUSION_DISABLE);
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if (rev == 0x11)
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO | HID1_ENABLE_BR_KILL_LIMIT);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering
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// Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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reg_mask(SYS_IMP_APL_HID6, HID6_UP_CRD_TKN_INIT_C2_MASK, HID6_UP_CRD_TKN_INIT_C2(0));
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reg_set(SYS_IMP_APL_HID7, HID7_FORCE_NONSPEC_IF_STEPPING |
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HID7_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_INVALID_AND_MP_VALID);
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reg_mask(SYS_IMP_APL_HID7, HID7_FORCE_NONSPEC_TARGET_TIMER_SEL_MASK,
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HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(3));
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reg_set(SYS_IMP_APL_HID9,
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HID9_TSO_SERIALIZE_VLD_MICROOPS | HID9_FIX_BUG_51667805 | HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID9, HID9_TSO_SERIALIZE_VLD_MICROOPS | HID9_FIX_BUG_51667805);
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reg_set(SYS_IMP_APL_HID18, HID18_HVC_SPECULATION_DISABLE);
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reg_clr(SYS_IMP_APL_HID21, HID21_ENABLE_LDREX_FILL_REPLY);
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}
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static void init_t8103_firestorm(int rev)
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{
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init_m1_firestorm();
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reg_mask(SYS_IMP_APL_HID6, HID6_UP_CRD_TKN_INIT_C2_MASK, HID6_UP_CRD_TKN_INIT_C2(0));
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if (rev >= 0x10) {
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID11, HID11_ENABLE_FIX_UC_55719865);
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}
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if (rev == 0x11)
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO | HID1_ENABLE_BR_KILL_LIMIT);
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if (rev >= 0x11)
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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}
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reg_clr(SYS_IMP_APL_HID21, HID21_ENABLE_LDREX_FILL_REPLY);
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static void init_t6000_firestorm(int rev)
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{
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init_m1_firestorm();
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init_common();
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID11, HID11_ENABLE_FIX_UC_55719865);
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if (rev >= 0x10) {
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO | HID1_ENABLE_BR_KILL_LIMIT);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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}
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}
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static void init_t6001_firestorm(int rev)
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{
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init_m1_firestorm();
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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reg_set(SYS_IMP_APL_HID9, HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID11, HID11_ENABLE_FIX_UC_55719865);
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if (rev >= 0x10) {
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_BR_KILL_LIMIT);
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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}
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}
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const char *init_cpu(void)
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@ -155,25 +174,33 @@ const char *init_cpu(void)
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switch (part) {
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case MIDR_PART_T8103_FIRESTORM:
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case MIDR_PART_T6000_FIRESTORM:
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case MIDR_PART_T6001_FIRESTORM:
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cpu = "M1 Firestorm";
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init_m1_firestorm(rev);
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init_t8103_firestorm(rev);
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break;
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case MIDR_PART_T6000_FIRESTORM:
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cpu = "M1 Pro Firestorm";
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init_t6000_firestorm(rev);
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break;
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case MIDR_PART_T6001_FIRESTORM:
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cpu = "M1 Max Firestorm";
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init_t6001_firestorm(rev);
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break;
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case MIDR_PART_T8103_ICESTORM:
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cpu = "M1 Icestorm";
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init_m1_icestorm(rev);
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init_m1_icestorm();
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break;
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case MIDR_PART_T6000_ICESTORM:
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cpu = "M1 Pro Icestorm";
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init_m1_icestorm(rev);
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init_m1_icestorm();
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break;
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case MIDR_PART_T6001_ICESTORM:
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cpu = "M1 Max Icestorm";
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init_m1_icestorm(rev);
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init_m1_icestorm();
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break;
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default:
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@ -181,6 +208,17 @@ const char *init_cpu(void)
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break;
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}
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int core = mrs(MPIDR_EL1) & 0xff;
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// Unknown, related to SMP?
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msr(s3_4_c15_c5_0, core);
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msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
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// Enable IRQs (at least necessary on t600x)
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msr(s3_4_c15_c10_4, 0);
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sysop("isb");
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/* Unmask external IRQs, set WFI mode to up (2) */
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reg_mask(SYS_IMP_APL_CYC_OVRD,
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CYC_OVRD_FIQ_MODE_MASK | CYC_OVRD_IRQ_MODE_MASK | CYC_OVRD_WFI_MODE_MASK,
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@ -68,8 +68,9 @@
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#define HID10_FORCE_WAIT_STATE_DRAIN_UC BIT(32)
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#define HID10_DISABLE_ZVA_TEMPORAL_TSO BIT(49)
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#define SYS_IMP_APL_HID11 sys_reg(3, 0, 15, 11, 0)
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#define HID11_DISABLE_LD_NT_WIDGET BIT(59)
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#define SYS_IMP_APL_HID11 sys_reg(3, 0, 15, 11, 0)
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#define HID11_ENABLE_FIX_UC_55719865 BIT(15)
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#define HID11_DISABLE_LD_NT_WIDGET BIT(59)
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#define SYS_IMP_APL_HID13 sys_reg(3, 0, 15, 14, 0)
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#define HID13_PRE_CYCLES(x) (((unsigned long)x) << 14)
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