mirror of
https://github.com/AsahiLinux/m1n1
synced 2024-11-10 09:44:13 +00:00
chickens: Refactor and update M1 bits
This adds some missing fixes for M1/T8103 and reworks the code to split off common parts, and also handle per-revision bits. Signed-off-by: Hector Martin <marcan@marcan.st>
This commit is contained in:
Hector Martin
parent
7ff48f6201
commit
ed21a80bc3
3 changed files with 120 additions and 73 deletions
112
src/chickens.c
112
src/chickens.c
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@ -6,20 +6,26 @@
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#include "utils.h"
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/* Part IDs in MIDR_EL1 */
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#define MIDR_PART_M1_ICESTORM 34
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#define MIDR_PART_M1_FIRESTORM 35
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#define MIDR_PART_A14_ICESTORM 0x20
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#define MIDR_PART_A14_FIRESTORM 0x21
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#define MIDR_PART_M1_ICESTORM 0x22
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#define MIDR_PART_M1_FIRESTORM 0x23
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void init_m1_common(void)
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#define MIDR_REV_LOW GENMASK(3, 0)
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#define MIDR_PART GENMASK(15, 4)
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#define MIDR_REV_HIGH GENMASK(23, 20)
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void init_common(void)
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{
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int core = mrs(MPIDR_EL1) & 0xff;
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// Unknown, related to SMP?
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msr(s3_4_c15_c5_0, core);
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msr(s3_4_c15_c1_4, 0x100);
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msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
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sysop("isb");
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}
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void init_m1_icestorm(void)
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void init_common_icestorm(void)
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{
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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@ -32,22 +38,11 @@ void init_m1_icestorm(void)
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// FIXME: do we actually need this?
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reg_set(SYS_IMP_APL_EHID20, EHID20_TRAP_SMC);
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reg_set(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER |
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EHID20_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_NE_BLK_RTR_POINTER);
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reg_mask(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL_MASK,
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EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL(3));
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init_m1_common();
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}
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void init_m1_firestorm(void)
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void init_common_firestorm(void)
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{
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// "Cross-beat Crypto(AES/PMUL) ICache fusion is not disabled for branch
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// uncondtional "recoded instruction."
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reg_set(SYS_IMP_APL_HID0,
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HID0_SAME_PG_POWER_OPTIMIZATION | HID0_FETCH_WIDTH_DISABLE | HID0_CACHE_FUSION_DISABLE);
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reg_set(SYS_IMP_APL_HID0, HID0_SAME_PG_POWER_OPTIMIZATION);
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// FIXME: do we actually need this?
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reg_set(SYS_IMP_APL_HID1, HID1_TRAP_SMC);
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@ -57,6 +52,56 @@ void init_m1_firestorm(void)
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// "Post-silicon tuning of STNT widget contiguous counter threshold"
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reg_mask(SYS_IMP_APL_HID4, HID4_STNT_COUNTER_THRESHOLD_MASK, HID4_STNT_COUNTER_THRESHOLD(3));
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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reg_set(SYS_IMP_APL_HID9, HID9_TSO_ALLOW_DC_ZVA_WC);
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reg_set(SYS_IMP_APL_HID11, HID11_DISABLE_LD_NT_WIDGET);
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// "configure dummy cycles to work around incorrect temp sensor readings on
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// NEX power gating"
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reg_mask(SYS_IMP_APL_HID13, HID13_PRE_CYCLES_MASK, HID13_PRE_CYCLES(4));
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// Best bit names...
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// Maybe: "RF bank and Multipass conflict forward progress widget does not
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// handle 3+ cycle livelock"
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reg_set(SYS_IMP_APL_HID16, HID16_SPAREBIT0 | HID16_SPAREBIT3 | HID16_ENABLE_MPX_PICK_45 |
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HID16_ENABLE_MP_CYCLONE_7);
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}
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void init_m1_icestorm(int rev)
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{
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UNUSED(rev);
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init_common_icestorm();
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reg_set(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER |
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EHID20_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_NE_BLK_RTR_POINTER);
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reg_mask(SYS_IMP_APL_EHID20, EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL_MASK,
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EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL(3));
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init_common();
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}
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void init_m1_firestorm(int rev)
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{
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if (rev < 0x10)
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printf(" Revisions <0x10 not supported!\n");
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init_common_firestorm();
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// "Cross-beat Crypto(AES/PMUL) ICache fusion is not disabled for branch
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// uncondtional "recoded instruction."
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reg_set(SYS_IMP_APL_HID0, HID0_FETCH_WIDTH_DISABLE | HID0_CACHE_FUSION_DISABLE);
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if (rev == 0x11)
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reg_set(SYS_IMP_APL_HID1, HID1_ENABLE_MDSB_STALL_PIPELINE_ECO | HID1_ENABLE_BR_KILL_LIMIT);
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reg_set(SYS_IMP_APL_HID4,
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HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE | HID4_ENABLE_LFSR_STALL_STQ_REPLAY);
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// "Sibling Merge in LLC can cause UC load to violate ARM Memory Ordering
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// Rules."
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reg_set(SYS_IMP_APL_HID5, HID5_DISABLE_FILL_2C_MERGE);
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@ -70,25 +115,16 @@ void init_m1_firestorm(void)
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HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(3));
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reg_set(SYS_IMP_APL_HID9,
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HID9_TSO_ALLOW_DC_ZVA_WC | HID9_TSO_SERIALIZE_VLD_MICROOPS | HID9_FIX_BUG_51667805);
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reg_set(SYS_IMP_APL_HID11, HID11_DISABLE_LD_NT_WIDGET);
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// "configure dummy cycles to work around incorrect temp sensor readings on
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// NEX power gating"
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reg_mask(SYS_IMP_APL_HID13, HID13_PRE_CYCLES_MASK, HID13_PRE_CYCLES(4));
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// Best bit names...
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// Maybe: "RF bank and Multipass conflict forward progress widget does not
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// handle 3+ cycle livelock"
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reg_set(SYS_IMP_APL_HID16, HID16_SPAREBIT0 | HID16_SPAREBIT3 | HID16_ENABLE_MPX_PICK_45 |
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HID16_ENABLE_MP_CYCLONE_7);
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HID9_TSO_SERIALIZE_VLD_MICROOPS | HID9_FIX_BUG_51667805 | HID9_FIX_BUG_55719865);
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reg_set(SYS_IMP_APL_HID18, HID18_HVC_SPECULATION_DISABLE);
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if (rev >= 0x11)
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reg_set(SYS_IMP_APL_HID18, HID18_SPAREBIT17);
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reg_clr(SYS_IMP_APL_HID21, HID21_ENABLE_LDREX_FILL_REPLY);
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init_m1_common();
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init_common();
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}
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const char *init_cpu(void)
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@ -103,21 +139,25 @@ const char *init_cpu(void)
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else
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reg_set(SYS_IMP_APL_HID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
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int part = (mrs(MIDR_EL1) >> 4) & 0xfff;
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uint64_t midr = mrs(MIDR_EL1);
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int part = FIELD_GET(MIDR_PART, midr);
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int rev = (FIELD_GET(MIDR_REV_HIGH, midr) << 4) | FIELD_GET(MIDR_REV_LOW, midr);
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printf(" CPU part: 0x%x rev: 0x%x\n", part, rev);
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switch (part) {
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case MIDR_PART_M1_FIRESTORM:
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cpu = "M1 Firestorm";
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init_m1_firestorm();
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init_m1_firestorm(rev);
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break;
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case MIDR_PART_M1_ICESTORM:
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cpu = "M1 Icestorm";
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init_m1_icestorm();
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init_m1_icestorm(rev);
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break;
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default:
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uart_puts("Unknown CPU type");
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uart_puts(" Unknown CPU type");
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break;
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}
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@ -9,80 +9,87 @@
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#define SYS_IMP_APL_ACTLR_EL12 sys_reg(3, 6, 15, 14, 6)
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#define SYS_IMP_APL_AMX_CTL_EL1 sys_reg(3, 4, 15, 1, 4)
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#define SYS_IMP_APL_AMX_CTL_EL2 sys_reg(3, 4, 15, 4, 7)
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#define AMX_CTL_EN BIT(63)
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#define AMX_CTL_EN_EL1 BIT(62)
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/* HID registers */
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#define SYS_IMP_APL_HID0 sys_reg(3, 0, 15, 0, 0)
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#define HID0_FETCH_WIDTH_DISABLE (1UL << 28)
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#define HID0_CACHE_FUSION_DISABLE (1UL << 36)
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#define HID0_SAME_PG_POWER_OPTIMIZATION (1UL << 45)
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#define HID0_FETCH_WIDTH_DISABLE BIT(28)
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#define HID0_CACHE_FUSION_DISABLE BIT(36)
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#define HID0_SAME_PG_POWER_OPTIMIZATION BIT(45)
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#define SYS_IMP_APL_HID1 sys_reg(3, 0, 15, 1, 0)
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#define HID1_TRAP_SMC (1UL << 54)
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#define SYS_IMP_APL_HID1 sys_reg(3, 0, 15, 1, 0)
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#define HID1_TRAP_SMC BIT(54)
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#define HID1_ENABLE_MDSB_STALL_PIPELINE_ECO BIT(58)
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#define HID1_ENABLE_BR_KILL_LIMIT BIT(60)
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#define SYS_IMP_APL_HID3 sys_reg(3, 0, 15, 3, 0)
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#define HID3_DEV_PCIE_THROTTLE_ENABLE (1UL << 63)
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#define HID3_DISABLE_ARBITER_FIX_BIF_CRD (1UL << 44)
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#define HID3_DEV_PCIE_THROTTLE_ENABLE BIT(63)
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#define HID3_DISABLE_ARBITER_FIX_BIF_CRD BIT(44)
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#define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0)
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#define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1)
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#define HID4_DISABLE_DC_MVA (1UL << 11)
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#define HID4_DISABLE_DC_SW_L2_OPS (1UL << 44)
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#define HID4_STNT_COUNTER_THRESHOLD(x) (((unsigned long)x) << 40)
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#define HID4_STNT_COUNTER_THRESHOLD_MASK (3UL << 40)
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#define SYS_IMP_APL_HID4 sys_reg(3, 0, 15, 4, 0)
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#define SYS_IMP_APL_EHID4 sys_reg(3, 0, 15, 4, 1)
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#define HID4_DISABLE_DC_MVA BIT(11)
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#define HID4_DISABLE_DC_SW_L2_OPS BIT(44)
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#define HID4_STNT_COUNTER_THRESHOLD(x) (((unsigned long)x) << 40)
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#define HID4_STNT_COUNTER_THRESHOLD_MASK (3UL << 40)
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#define HID4_ENABLE_LFSR_STALL_LOAD_PIPE_2_ISSUE BIT(49)
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#define HID4_ENABLE_LFSR_STALL_STQ_REPLAY BIT(53)
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#define SYS_IMP_APL_HID5 sys_reg(3, 0, 15, 5, 0)
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#define HID5_DISABLE_FILL_2C_MERGE (1UL << 61)
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#define HID5_DISABLE_FILL_2C_MERGE BIT(61)
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#define SYS_IMP_APL_HID6 sys_reg(3, 0, 15, 6, 0)
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#define HID6_UP_CRD_TKN_INIT_C2(x) (((unsigned long)x) << 5)
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#define HID6_UP_CRD_TKN_INIT_C2_MASK (0x1FUL << 5)
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#define SYS_IMP_APL_HID7 sys_reg(3, 0, 15, 7, 0)
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#define HID7_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_INVALID_AND_MP_VALID (1UL << 16)
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#define HID7_FORCE_NONSPEC_IF_STEPPING (1UL << 20)
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#define HID7_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_INVALID_AND_MP_VALID BIT(16)
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#define HID7_FORCE_NONSPEC_IF_STEPPING BIT(20)
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#define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL(x) (((unsigned long)x) << 24)
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#define HID7_FORCE_NONSPEC_TARGET_TIMER_SEL_MASK (3UL << 24)
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#define SYS_IMP_APL_HID9 sys_reg(3, 0, 15, 9, 0)
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#define HID9_TSO_ALLOW_DC_ZVA_WC (1UL << 26)
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#define HID9_TSO_SERIALIZE_VLD_MICROOPS (1UL << 29)
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#define HID9_FIX_BUG_51667805 (1UL << 48)
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#define HID9_TSO_ALLOW_DC_ZVA_WC BIT(26)
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#define HID9_TSO_SERIALIZE_VLD_MICROOPS BIT(29)
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#define HID9_FIX_BUG_51667805 BIT(48)
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#define HID9_FIX_BUG_55719865 BIT(55)
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#define SYS_IMP_APL_EHID9 sys_reg(3, 0, 15, 9, 1)
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#define EHID9_DEV_THROTTLE_2_ENABLE (1UL << 5)
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#define EHID9_DEV_THROTTLE_2_ENABLE BIT(5)
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#define SYS_IMP_APL_EHID10 sys_reg(3, 0, 15, 10, 1)
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#define HID10_FORCE_WAIT_STATE_DRAIN_UC (1UL << 32)
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#define HID10_DISABLE_ZVA_TEMPORAL_TSO (1UL << 49)
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#define HID10_FORCE_WAIT_STATE_DRAIN_UC BIT(32)
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#define HID10_DISABLE_ZVA_TEMPORAL_TSO BIT(49)
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#define SYS_IMP_APL_HID11 sys_reg(3, 0, 15, 11, 0)
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#define HID11_DISABLE_LD_NT_WIDGET (1UL << 59)
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#define HID11_DISABLE_LD_NT_WIDGET BIT(59)
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#define SYS_IMP_APL_HID13 sys_reg(3, 0, 15, 14, 0)
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#define HID13_PRE_CYCLES(x) (((unsigned long)x) << 14)
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#define HID13_PRE_CYCLES_MASK (0xFUL << 14)
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#define SYS_IMP_APL_HID16 sys_reg(3, 0, 15, 15, 2)
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#define HID16_SPAREBIT0 (1UL << 56)
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#define HID16_SPAREBIT3 (1UL << 59)
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#define HID16_ENABLE_MPX_PICK_45 (1UL << 61)
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#define HID16_ENABLE_MP_CYCLONE_7 (1UL << 62)
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#define HID16_SPAREBIT0 BIT(56)
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#define HID16_SPAREBIT3 BIT(59)
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#define HID16_ENABLE_MPX_PICK_45 BIT(61)
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#define HID16_ENABLE_MP_CYCLONE_7 BIT(62)
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#define SYS_IMP_APL_HID18 sys_reg(3, 0, 15, 11, 2)
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#define HID18_HVC_SPECULATION_DISABLE (1UL << 14)
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#define HID18_HVC_SPECULATION_DISABLE BIT(14)
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#define HID18_SPAREBIT17 BIT(49)
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#define SYS_IMP_APL_EHID20 sys_reg(3, 0, 15, 1, 2)
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#define EHID20_TRAP_SMC (1UL << 8)
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#define EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER (1UL << 15)
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#define EHID20_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_NE_BLK_RTR_POINTER (1UL << 16)
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#define EHID20_TRAP_SMC BIT(8)
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#define EHID20_FORCE_NONSPEC_IF_OLDEST_REDIR_VALID_AND_OLDER BIT(15)
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#define EHID20_FORCE_NONSPEC_IF_SPEC_FLUSH_POINTER_NE_BLK_RTR_POINTER BIT(16)
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#define EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL(x) (((unsigned long)x) << 21)
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#define EHID20_FORCE_NONSPEC_TARGETED_TIMER_SEL_MASK (3UL << 21)
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#define SYS_IMP_APL_HID21 sys_reg(3, 0, 15, 1, 3)
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#define HID21_ENABLE_LDREX_FILL_REPLY (1UL << 19)
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#define HID21_ENABLE_LDREX_FILL_REPLY BIT(19)
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#define SYS_IMP_APL_PMCR0 sys_reg(3, 1, 15, 0, 0)
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#define PMCR0_CNT_EN_MASK (MASK(8) | GENMASK(33, 32))
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@ -122,9 +129,9 @@
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#define SYS_IMP_APL_L2C_ERR_STS sys_reg(3, 3, 15, 8, 0)
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#define L2C_ERR_STS_RECURSIVE_FAULT (1UL << 1)
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#define L2C_ERR_STS_ACCESS_FAULT (1UL << 7)
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#define L2C_ERR_STS_ENABLE_W1C (1UL << 56)
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#define L2C_ERR_STS_RECURSIVE_FAULT BIT(1)
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#define L2C_ERR_STS_ACCESS_FAULT BIT(7)
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#define L2C_ERR_STS_ENABLE_W1C BIT(56)
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#define SYS_IMP_APL_L2C_ERR_ADR sys_reg(3, 3, 15, 9, 0)
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#define SYS_IMP_APL_L2C_ERR_INF sys_reg(3, 3, 15, 10, 0)
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@ -91,9 +91,9 @@ void _start_c(void *boot_args, void *base)
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}
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uart_puts("Initializing");
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printf("CPU init... ");
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printf("CPU init (MIDR: 0x%lx)...\n", mrs(MIDR_EL1));
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const char *type = init_cpu();
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printf("CPU: %s\n\n", type);
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printf(" CPU: %s\n\n", type);
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printf("boot_args at %p\n", boot_args);
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