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f5a2425919
The 7610 and related parts have an L2IP bit in the L2CR that is monitored to signal when the L2 cache invalidate is complete whereas the 7450 and related parts utilize L2I for this purpose. However, the current code does not account for this difference. Additionally the 86xx L2 cache invalidate code used an "andi" instruction where an "andis" instruction should have been used. This patch addresses both of these bugs. Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com> Acked-By: Jon Loeliger <jdl@freescale.com> |
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| .. | ||
| cache.S | ||
| config.mk | ||
| cpu.c | ||
| cpu_init.c | ||
| fdt.c | ||
| interrupts.c | ||
| Makefile | ||
| spd_sdram.c | ||
| speed.c | ||
| start.S | ||
| traps.c | ||