Lokesh Vutla ea8eff1fe0 arm: dra7xx: clock: Add the dplls data ... A new DPLL DDR is added in DRA7XX socs. Now clocks to EMIF CD is from DPLL DDR. So DPLL DDR should be locked before initializing RAM. Also adding other dpll data which are different from OMAP5 ES2.0. SYS_CLK running at 20MHz is introduced in DRA7xx socs. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>		2013-03-11 11:06:11 -04:00
..
config.mk	mkimage: Add OMAP boot image support	2011-08-03 12:49:20 +02:00
emif.c	omap5: emif: Add emif/ddr configurations required for omap5 evm	2011-11-15 22:25:50 +01:00
hw_data.c	arm: dra7xx: clock: Add the dplls data	2013-03-11 11:06:11 -04:00
hwinit.c	ARM: OMAP4+: Make control module register structure generic	2013-03-11 11:06:10 -04:00
Makefile	ARM: OMAP4+: Clean up the pmic code	2013-03-11 11:06:10 -04:00
prcm-regs.c	arm: dra7xx: clock: Add the prcm changes	2013-03-11 11:06:11 -04:00
sdram_elpida.c	ARM: OMAP4+: Cleanup emif specific files	2013-03-11 11:06:10 -04:00