Rick Chen dda00ae4ef riscv: ax25: Andes specific cache shall only support in M-mode ... Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>		2019-04-08 09:45:08 +08:00
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cpu	riscv: ax25: Andes specific cache shall only support in M-mode	2019-04-08 09:45:08 +08:00
dts	riscv: Remove ae350.dts	2018-12-18 09:56:27 +08:00
include/asm	riscv: Add a SYSCON driver for Andestech's PLMT	2019-04-08 09:45:08 +08:00
lib	riscv: Add a SYSCON driver for Andestech's PLMT	2019-04-08 09:45:08 +08:00
config.mk	riscv: qemu: define standalone load address	2019-01-15 09:36:31 +08:00
Kconfig	riscv: Add a SYSCON driver for Andestech's PLMT	2019-04-08 09:45:08 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00