Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-06 05:04:26 +00:00
Code Issues Projects Releases Packages Wiki Activity
u-boot/board/freescale/ls1043ardb
History
macro.wave.z@gmail.com c151cb5b51 ARMv8: LS1043A: Enable LS1043A default PSCI support 
A most basic PSCI implementation with only one psci_version is added for
LS1043A, this can verify the generic PSCI framework, and more platform specific
implementation will be added later.

Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2016-12-15 11:57:56 -08:00
..
cpld.c armv8/ls1043ardb: fix the limitation of using 'cpld reset' 2016-05-18 08:51:44 -07:00
cpld.h armv8/ls1043ardb: fix the limitation of using 'cpld reset' 2016-05-18 08:51:44 -07:00
ddr.c fsl/board/ddr: optimize board-specific cpo for erratum A-009942 2016-12-15 11:56:39 -08:00
ddr.h board/freescale: Update ddr clk_adjust 2016-06-03 14:06:57 -07:00
eth.c armv8/ls1043a: Add Fman support 2015-10-29 10:34:01 -07:00
Kconfig ARMv8: LS1043A: Enable LS1043A default PSCI support 2016-12-15 11:57:56 -08:00
ls1043ardb.c fsl-layerscape: Add workaround for PCIe erratum A010315 2016-09-14 14:07:13 -07:00
ls1043ardb_pbi.cfg armv8/ls1043ardb: Add nand boot support 2015-10-29 10:34:01 -07:00
ls1043ardb_rcw_nand.cfg armv8/ls1043ardb/rcw: change core frequency to 1600MHz 2015-12-17 08:52:18 +08:00
ls1043ardb_rcw_sd.cfg armv8/ls1043ardb/rcw: change core frequency to 1600MHz 2015-12-17 08:52:18 +08:00
MAINTAINERS board/freescale: Update MAINTAINERS files 2016-08-02 09:47:34 -07:00
Makefile armv8/ls1043a: Add Fman support 2015-10-29 10:34:01 -07:00
README armv8: fsl-layerscape: Organize SoC overview at common location 2016-06-03 14:12:50 -07:00

README 

Overview
--------
The LS1043A Reference Design Board (RDB) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS1043A
LayerScape Architecture processor. The LS1043ARDB provides SW development
platform for the Freescale LS1043A processor series, with a complete
debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.

LS1043A SoC Overview
--------------------
Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
SoC overview.

 LS1043ARDB board Overview
 -----------------------
 - SERDES Connections, 4 lanes supporting:
      - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
        standard PCIe card
      - QSGMII with x4 RJ45 connector
      - XFI with x1 RJ45 connector
 - DDR Controller
     - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
 -IFC/Local Bus
    - One 128MB NOR flash 16-bit data bus
    - One 512 MB NAND flash with ECC support
    - CPLD connection
 - USB 3.0
    - Two super speed USB 3.0 Type A ports
 - SDHC: connects directly to a full SD/MMC slot
 - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
 - 4 I2C controllers
 - UART
   - Two 4-pin serial ports at up to 115.2 Kbit/s
   - Two DB9 D-Type connectors supporting one Serial port each
 - ARM JTAG support

Memory map from core's view
----------------------------
Start Address	End Address	Description		Size
0x00_0000_0000	0x00_000F_FFFF	Secure Boot ROM		1MB
0x00_0100_0000	0x00_0FFF_FFFF	CCSRBAR			240MB
0x00_1000_0000	0x00_1000_FFFF	OCRAM0			64KB
0x00_1001_0000	0x00_1001_FFFF	OCRAM1			64KB
0x00_2000_0000	0x00_20FF_FFFF	DCSR			16MB
0x00_6000_0000	0x00_67FF_FFFF	IFC - NOR Flash		128MB
0x00_7E80_0000	0x00_7E80_FFFF	IFC - NAND Flash	64KB
0x00_7FB0_0000	0x00_7FB0_0FFF	IFC - FPGA		4KB
0x00_8000_0000	0x00_FFFF_FFFF	DRAM1			2GB

Booting Options
---------------
a) NOR boot
b) NAND boot
c) SD boot