Andre Przywara 7400d34ba9 riscv: semihosting: replace inline assembly with assembly file ... So far we used inline assembly to inject the actual instruction that triggers the semihosting service. While this sounds elegant, as it's really only about a few instructions, it has some serious downsides: - We need some barriers in place to force the compiler to issue writes to a data structure before issuing the trap instruction. - We need to convince the compiler to actually fill the structures that we use pointers to. - We need a memory clobber to avoid the compiler caching the data in those structures, when semihosting writes data back. - We need register arguments to make sure the function ID and the pointer land in the right registers. This is all doable, but fragile and somewhat cumbersome. Since we now have a separate function in an extra file anyway, we can do away with all the magic and just write that in an actual assembler. This is much more readable and robust. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Sean Anderson <sean.anderson@seco.com>		2023-03-06 19:24:34 -05:00
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cpu	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
dts	Prepare v2023.04-rc3	2023-02-27 17:28:21 -05:00
include/asm	riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()	2023-02-17 19:07:48 +08:00
lib	riscv: semihosting: replace inline assembly with assembly file	2023-03-06 19:24:34 -05:00
config.mk	Convert CONFIG_STANDALONE_LOAD_ADDR to Kconfig	2022-12-22 10:31:48 -05:00
Kconfig	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00