Heinrich Schuchardt 9757cae991 riscv: allow resume after exception ... If CSRs like seed are readable by S-mode, may not be determinable by S-mode. For safe driver probing allow to resume via a longjmp after an exception. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2023-11-02 16:22:06 +08:00
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cpu	riscv: Align the trap handler to 64 bytes	2023-11-02 15:15:46 +08:00
dts	sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6	2023-10-22 01:12:26 +01:00
include/asm	riscv: cpu: jh7110: Add gpio helper macros	2023-11-02 15:44:56 +08:00
lib	riscv: allow resume after exception	2023-11-02 16:22:06 +08:00
config.mk	riscv: Support CONFIG_REMAKE_ELF	2023-04-20 20:45:08 +08:00
Kconfig	riscv: Sort target configs alphabetically	2023-11-02 15:15:33 +08:00
Makefile	riscv: Add Zbb support for building U-Boot	2023-10-19 17:29:50 +08:00