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powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code

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Remove duplicated code in corenet_ds boards and utilize the common
fsl_pcie_init_board().

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-01-06 10:39:52 -06:00
parent 2d0a054d55
commit e650ae1bb7
1 changed files with 2 additions and 116 deletions
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118
board/freescale/corenet_ds/pci.c
View file

@ -1,5 +1,5 @@
/*
* Copyright 2007-2010 Freescale Semiconductor, Inc.
* Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* See file CREDITS for list of people who contributed to this
* project.
@ -28,123 +28,9 @@
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
#ifdef CONFIG_PCIE1
static struct pci_controller pcie1_hose;
#endif
#ifdef CONFIG_PCIE2
static struct pci_controller pcie2_hose;
#endif
#ifdef CONFIG_PCIE3
static struct pci_controller pcie3_hose;
#endif
#ifdef CONFIG_PCIE4
static struct pci_controller pcie4_hose;
#endif
void pci_init_board(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct fsl_pci_info pci_info[4];
u32 devdisr;
int first_free_busno = 0;
int num = 0;
int pcie_ep, pcie_configured;
devdisr = in_be32(&gur->devdisr);
debug (" pci_init_board: devdisr=%x\n", devdisr);
#ifdef CONFIG_PCIE1
pcie_configured = is_serdes_configured(PCIE1);
if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE1)) {
set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M,
LAW_TRGT_IF_PCIE_1);
set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K,
LAW_TRGT_IF_PCIE_1);
SET_STD_PCIE_INFO(pci_info[num], 1);
pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie1_hose, first_free_busno);
} else {
printf("PCIE1: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
#endif
#ifdef CONFIG_PCIE2
pcie_configured = is_serdes_configured(PCIE2);
if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE2)) {
set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M,
LAW_TRGT_IF_PCIE_2);
set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K,
LAW_TRGT_IF_PCIE_2);
SET_STD_PCIE_INFO(pci_info[num], 2);
pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie2_hose, first_free_busno);
} else {
printf("PCIE2: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
#endif
#ifdef CONFIG_PCIE3
pcie_configured = is_serdes_configured(PCIE3);
if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE3)) {
set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M,
LAW_TRGT_IF_PCIE_3);
set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K,
LAW_TRGT_IF_PCIE_3);
SET_STD_PCIE_INFO(pci_info[num], 3);
pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie3_hose, first_free_busno);
} else {
printf("PCIE3: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
#endif
#ifdef CONFIG_PCIE4
pcie_configured = is_serdes_configured(PCIE4);
if (pcie_configured && !(devdisr & FSL_CORENET_DEVDISR_PCIE4)) {
set_next_law(CONFIG_SYS_PCIE4_MEM_PHYS, LAW_SIZE_512M,
LAW_TRGT_IF_PCIE_4);
set_next_law(CONFIG_SYS_PCIE4_IO_PHYS, LAW_SIZE_64K,
LAW_TRGT_IF_PCIE_4);
SET_STD_PCIE_INFO(pci_info[num], 4);
pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
printf("PCIE4: connected to as %s (base addr %lx)\n",
pcie_ep ? "End Point" : "Root Complex",
pci_info[num].regs);
first_free_busno = fsl_pci_init_port(&pci_info[num++],
&pcie4_hose, first_free_busno);
} else {
printf("PCIE4: disabled\n");
}
#else
setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
#endif
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)