Marek Vasut 99c7e03119 clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching ... Do not cache the single CPG MODE register bit 12, instead cache the entire register value, and only pick the matching bit from the cached value when core clock of type MDSEL or PE are used. Both MDSEL and PE clock type currently define .offset field as 12 on Gen3, which means this code will use bit 12 on Gen3 again, however there are additional clock on Gen4 which use different bits, and having this flexibility in place now will be useful when adding Gen4. No functional change. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>		2023-03-18 12:02:38 +01:00
..
clk-rcar-gen2.c	clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_table	2023-02-02 01:49:20 +01:00
clk-rcar-gen3.c	clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching	2023-03-18 12:02:38 +01:00
Kconfig	clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver	2023-03-10 17:46:09 +01:00
Makefile	clk: renesas: rcar-gen3: Factor out CPG library	2023-02-02 01:49:20 +01:00
r8a774a1-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a774b1-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a774c0-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a774e1-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a779a0-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a7790-cpg-mssr.c	clk: renesas: Make reset controller modemr register offset configurable	2021-05-21 15:00:17 +02:00
r8a7791-cpg-mssr.c	clk: renesas: Make reset controller modemr register offset configurable	2021-05-21 15:00:17 +02:00
r8a7792-cpg-mssr.c	clk: renesas: Make reset controller modemr register offset configurable	2021-05-21 15:00:17 +02:00
r8a7794-cpg-mssr.c	clk: renesas: Make reset controller modemr register offset configurable	2021-05-21 15:00:17 +02:00
r8a7795-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a7796-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a77965-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a77970-cpg-mssr.c	clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI	2023-02-02 01:49:20 +01:00
r8a77980-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a77990-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
r8a77995-cpg-mssr.c	clk: renesas: Add and enable CPG reset driver	2023-02-02 01:49:20 +01:00
rcar-cpg-lib.c	clk: renesas: rcar-gen3: Factor out CPG library	2023-02-02 01:49:20 +01:00
rcar-cpg-lib.h	clk: renesas: rcar-gen3: Factor out CPG library	2023-02-02 01:49:20 +01:00
rcar-gen2-cpg.h	clk: renesas: Make reset controller modemr register offset configurable	2021-05-21 15:00:17 +02:00
rcar-gen3-cpg.h	clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching	2023-03-18 12:02:38 +01:00
renesas-cpg-mssr.c	clk: renesas: Add R8A779A0 clock tables	2021-06-24 20:22:17 +02:00
renesas-cpg-mssr.h	clk: renesas: Add R8A779A0 clock tables	2021-06-24 20:22:17 +02:00