mirror of
https://github.com/AsahiLinux/u-boot
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d8132ae37a
On R-Car V3M (AKA R8A77970), the SD0CKCR is laid out differently than on
the other R-Car gen3 SoCs. Hence, new clock types are introduced
respectively.
Based on Linux commit 381081ffc294 ("clk: renesas: r8a77970: Add SD0H/SD0
clocks for SDHI") by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek: - Fix missing ~ in GENMASK(a, b), use clrsetbits_le32 instead
- Do not modify r8a77970-cpg-mssr.c much, drop enum r8a77970_clk_types
which is now part of common clock types in rcar-gen3-cpg.h instead
230 lines
7.5 KiB
C
230 lines
7.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Renesas R8A77970 CPG MSSR driver
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*
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* Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
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*
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* Based on the following driver from Linux kernel:
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* r8a7796 Clock Pulse Generator / Module Standby and Software Reset
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*
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* Copyright (C) 2016 Glider bvba
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <linux/bitops.h>
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#include <dt-bindings/clock/r8a77970-cpg-mssr.h>
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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#define CPG_SD0CKCR 0x0074
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
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/* External Input Clocks */
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CLK_EXTAL,
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CLK_EXTALR,
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/* Internal Core Clocks */
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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CLK_PLL3,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE
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};
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static const struct cpg_core_clk r8a77970_core_clks[] = {
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/* External Clock Inputs */
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DEF_INPUT("extal", CLK_EXTAL),
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DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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/* Core Clock Outputs */
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DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
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DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
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DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
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DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
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DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
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DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
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DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
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DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
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CLK_PLL1_DIV2),
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DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
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DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
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DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
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DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
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DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
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DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
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DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
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DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
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};
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static const struct mssr_mod_clk r8a77970_mod_clks[] = {
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DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
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DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
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DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
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DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
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DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
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DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
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DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
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DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
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DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
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DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
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DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
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DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
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DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
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DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
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DEF_MOD("cmt3", 300, R8A77970_CLK_R),
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DEF_MOD("cmt2", 301, R8A77970_CLK_R),
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DEF_MOD("cmt1", 302, R8A77970_CLK_R),
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DEF_MOD("cmt0", 303, R8A77970_CLK_R),
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DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
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DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
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DEF_MOD("rwdt", 402, R8A77970_CLK_R),
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DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
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DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
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DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
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DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
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DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
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DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
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DEF_MOD("thermal", 522, R8A77970_CLK_CP),
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DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
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DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
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DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
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DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
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DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
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DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
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DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
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DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
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DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
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DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
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DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
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DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
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DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
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DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
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DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
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DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
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DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
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DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
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DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
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DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
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DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
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DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
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DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
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DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
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};
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/*
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* CPG Clock Data
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*/
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz)
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*-------------------------------------------------
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* 0 0 0 16.66 x 1 x192 x192 x96
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* 0 0 1 16.66 x 1 x192 x192 x80
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* 0 1 0 20 x 1 x160 x160 x80
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* 0 1 1 20 x 1 x160 x160 x66
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* 1 0 0 27 / 2 x236 x236 x118
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* 1 0 1 27 / 2 x236 x236 x98
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* 1 1 0 33.33 / 2 x192 x192 x96
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* 1 1 1 33.33 / 2 x192 x192 x80
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*/
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#define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
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(((md) & BIT(13)) >> 12) | \
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(((md) & BIT(19)) >> 19))
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static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] = {
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/* EXTAL div PLL1 mult/div PLL3 mult/div */
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{ 1, 192, 1, 96, 1, },
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{ 1, 192, 1, 80, 1, },
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{ 1, 160, 1, 80, 1, },
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{ 1, 160, 1, 66, 1, },
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{ 2, 236, 1, 118, 1, },
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{ 2, 236, 1, 98, 1, },
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{ 2, 192, 1, 96, 1, },
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{ 2, 192, 1, 80, 1, },
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};
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static const struct mstp_stop_table r8a77970_mstp_table[] = {
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{ 0x00230000, 0x0, 0x00230000, 0 },
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{ 0x0be00000, 0x0, 0x0be00000, 0 },
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{ 0x04062fd8, 0x2080, 0x04062fd8, 0 },
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{ 0x00c0c0df, 0x0, 0x00c0c0df, 0 },
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{ 0x80000004, 0x180, 0x80000004, 0 },
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{ 0x00de0028, 0x0, 0x00de0028, 0 },
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{ 0x00800008, 0x0, 0x00800008, 0 },
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{ 0x09010000, 0x0, 0x09010000, 0 },
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{ 0x7ff21f00, 0x0, 0x7ff21f00, 0 },
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{ 0xf8025f84, 0x0, 0xf8025f84, 0 },
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{ 0x00000000, 0x0, 0x00000000, 0 },
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{ 0x00000000, 0x0, 0x00000000, 0 },
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};
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static const void *r8a77970_get_pll_config(const u32 cpg_mode)
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{
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return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
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}
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static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
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.core_clk = r8a77970_core_clks,
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.core_clk_size = ARRAY_SIZE(r8a77970_core_clks),
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.mod_clk = r8a77970_mod_clks,
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.mod_clk_size = ARRAY_SIZE(r8a77970_mod_clks),
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.mstp_table = r8a77970_mstp_table,
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.mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
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.reset_node = "renesas,r8a77970-rst",
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.reset_modemr_offset = CPG_RST_MODEMR,
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.extalr_node = "extalr",
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.mod_clk_base = MOD_CLK_BASE,
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.clk_extal_id = CLK_EXTAL,
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.clk_extalr_id = CLK_EXTALR,
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.get_pll_config = r8a77970_get_pll_config,
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};
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static const struct udevice_id r8a77970_cpg_ids[] = {
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{
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.compatible = "renesas,r8a77970-cpg-mssr",
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.data = (ulong)&r8a77970_cpg_mssr_info
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},
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{ }
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};
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U_BOOT_DRIVER(cpg_r8a77970) = {
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.name = "cpg_r8a77970",
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.id = UCLASS_NOP,
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.of_match = r8a77970_cpg_ids,
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.bind = gen3_cpg_bind,
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};
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