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b71129ca3b
The original H616 DDR3 ODT configuration code wrote board specific values into a sequence of paired registers. For LPDDR3 support we needed to special-case one group of registers, because for that DRAM type we need to write 0 into the lower register of each pair. That already made the code less readable. LPDDR4 support will make things even messier, so let's refactor that code now: We allow to write different values into the lower and upper half of each pair. The masking is moved into a macro, and use in each write statement. The effect is not as obvious yet, as we don't need the full flexibility at the moment, but the motivation will become clearer with LPDDR4 support. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Reviewed-by: Mikhail Kalashnikov <iuncuim@gmail.com> |
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| arc | ||
| arm | ||
| m68k | ||
| microblaze | ||
| mips | ||
| nios2 | ||
| powerpc | ||
| riscv | ||
| sandbox | ||
| sh | ||
| x86 | ||
| xtensa | ||
| .gitignore | ||
| Kconfig | ||
| Kconfig.nxp | ||
| u-boot-elf.lds | ||