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a74f0c7cb5
The ddr_regs struct was incorrectly offset after the dt0wiratio0 entry.
Correct this by documenting a missing register that will be used at some
point in the future (when write leveling is supported). Further, the
cmdNcs{force,delay} fields are undocumented and we have been setting
them to zero, remove. Next, setting of the
'DATAn_REG_PHY_USE_RANK0_DELAYS field belongs with the rest of the
ddr_data entries, so program it there. Finally, comment on how we are
configuring the DATA1 registers that correspond to the DATA0 (dt0)
registers defined in the struct.
Signed-off-by: Tom Rini <trini@ti.com>
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| .. | ||
| am33xx | ||
| exynos | ||
| highbank | ||
| imx-common | ||
| mx5 | ||
| mx6 | ||
| omap-common | ||
| omap3 | ||
| omap4 | ||
| omap5 | ||
| s5p-common | ||
| s5pc1xx | ||
| tegra2 | ||
| u8500 | ||
| cache_v7.c | ||
| config.mk | ||
| cpu.c | ||
| Makefile | ||
| start.S | ||
| syslib.c | ||