mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 18:59:44 +00:00
950a392464
Reverting became necessary after it turned out that the patches in the u-boot-arm repo were modified, and in some cases corrupted. This reverts the following commits:066bebd6357a837b7310c88ae20580a147e56f03d6674e0e2a8c8463cce4c98b47ad248bf69d81788c16cb0d3ba574a738521377b5583a1704dc2091Signed-off-by: Wolfgang Denk <wd@denx.de>
389 lines
10 KiB
C
389 lines
10 KiB
C
/*
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* NAND driver for TI DaVinci based boards.
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Based on Linux DaVinci NAND driver by TI. Original copyright follows:
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*/
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/*
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*
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* linux/drivers/mtd/nand/nand_davinci.c
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*
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* NAND Flash Driver
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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* ----------------------------------------------------------------------------
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* DaVinci board which utilizes the Samsung k9k2g08 part.
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*
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Modifications:
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ver. 1.0: Feb 2005, Vinod/Sudhakar
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-
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*
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*/
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#include <common.h>
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#ifdef CFG_USE_NAND
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#if !defined(CFG_NAND_LEGACY)
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#include <nand.h>
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#include <asm/arch/nand_defs.h>
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#include <asm/arch/emif_defs.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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struct nand_chip *this = mtd->priv;
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u_int32_t IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;
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IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);
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switch (cmd) {
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case NAND_CTL_SETCLE:
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IO_ADDR_W |= MASK_CLE;
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break;
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case NAND_CTL_SETALE:
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IO_ADDR_W |= MASK_ALE;
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break;
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}
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this->IO_ADDR_W = (void *)IO_ADDR_W;
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}
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/* Set WP on deselect, write enable on select */
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static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
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{
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#define GPIO_SET_DATA01 0x01c67018
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#define GPIO_CLR_DATA01 0x01c6701c
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#define GPIO_NAND_WP (1 << 4)
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#ifdef SONATA_BOARD_GPIOWP
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if (chip < 0) {
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REG(GPIO_CLR_DATA01) |= GPIO_NAND_WP;
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} else {
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REG(GPIO_SET_DATA01) |= GPIO_NAND_WP;
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}
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#endif
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}
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#ifdef CFG_NAND_HW_ECC
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#ifdef CFG_NAND_LARGEPAGE
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static struct nand_oobinfo davinci_nand_oobinfo = {
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.useecc = MTD_NANDECC_AUTOPLACE,
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.eccbytes = 12,
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.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
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.oobfree = { {2, 6}, {12, 12}, {28, 12}, {44, 12}, {60, 4} }
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};
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#elif defined(CFG_NAND_SMALLPAGE)
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static struct nand_oobinfo davinci_nand_oobinfo = {
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.useecc = MTD_NANDECC_AUTOPLACE,
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.eccbytes = 3,
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.eccpos = {0, 1, 2},
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.oobfree = { {6, 2}, {8, 8} }
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};
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#else
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#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
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#endif
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static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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emifregs emif_addr;
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int dummy;
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emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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dummy = emif_addr->NANDF1ECC;
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dummy = emif_addr->NANDF2ECC;
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dummy = emif_addr->NANDF3ECC;
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dummy = emif_addr->NANDF4ECC;
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emif_addr->NANDFCR |= (1 << 8);
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}
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static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
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{
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u_int32_t ecc = 0;
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emifregs emif_base_addr;
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emif_base_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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if (region == 1)
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ecc = emif_base_addr->NANDF1ECC;
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else if (region == 2)
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ecc = emif_base_addr->NANDF2ECC;
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else if (region == 3)
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ecc = emif_base_addr->NANDF3ECC;
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else if (region == 4)
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ecc = emif_base_addr->NANDF4ECC;
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return(ecc);
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}
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static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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u_int32_t tmp;
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int region, n;
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struct nand_chip *this = mtd->priv;
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n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
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region = 1;
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while (n--) {
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tmp = nand_davinci_readecc(mtd, region);
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*ecc_code++ = tmp;
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*ecc_code++ = tmp >> 16;
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*ecc_code++ = ((tmp >> 8) & 0x0f) | ((tmp >> 20) & 0xf0);
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region++;
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}
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return(0);
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}
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static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
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{
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u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
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ecc_buf[0] = ~(P64o(tmp) | P64e(tmp) | P32o(tmp) | P32e(tmp) | P16o(tmp) | P16e(tmp) | P8o(tmp) | P8e(tmp));
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ecc_buf[1] = ~(P1024o(tmp) | P1024e(tmp) | P512o(tmp) | P512e(tmp) | P256o(tmp) | P256e(tmp) | P128o(tmp) | P128e(tmp));
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ecc_buf[2] = ~( P4o(tmp) | P4e(tmp) | P2o(tmp) | P2e(tmp) | P1o(tmp) | P1e(tmp) | P2048o(tmp) | P2048e(tmp));
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}
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static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_int8_t *page_data)
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{
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u_int32_t i;
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u_int8_t tmp0_bit[8], tmp1_bit[8], tmp2_bit[8];
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u_int8_t comp0_bit[8], comp1_bit[8], comp2_bit[8];
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u_int8_t ecc_bit[24];
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u_int8_t ecc_sum = 0;
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u_int8_t find_bit = 0;
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u_int32_t find_byte = 0;
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int is_ecc_ff;
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is_ecc_ff = ((*ecc_nand == 0xff) && (*(ecc_nand + 1) == 0xff) && (*(ecc_nand + 2) == 0xff));
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nand_davinci_gen_true_ecc(ecc_nand);
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nand_davinci_gen_true_ecc(ecc_calc);
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for (i = 0; i <= 2; i++) {
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*(ecc_nand + i) = ~(*(ecc_nand + i));
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*(ecc_calc + i) = ~(*(ecc_calc + i));
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}
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for (i = 0; i < 8; i++) {
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tmp0_bit[i] = *ecc_nand % 2;
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*ecc_nand = *ecc_nand / 2;
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}
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for (i = 0; i < 8; i++) {
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tmp1_bit[i] = *(ecc_nand + 1) % 2;
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*(ecc_nand + 1) = *(ecc_nand + 1) / 2;
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}
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for (i = 0; i < 8; i++) {
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tmp2_bit[i] = *(ecc_nand + 2) % 2;
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*(ecc_nand + 2) = *(ecc_nand + 2) / 2;
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}
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for (i = 0; i < 8; i++) {
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comp0_bit[i] = *ecc_calc % 2;
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*ecc_calc = *ecc_calc / 2;
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}
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for (i = 0; i < 8; i++) {
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comp1_bit[i] = *(ecc_calc + 1) % 2;
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*(ecc_calc + 1) = *(ecc_calc + 1) / 2;
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}
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for (i = 0; i < 8; i++) {
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comp2_bit[i] = *(ecc_calc + 2) % 2;
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*(ecc_calc + 2) = *(ecc_calc + 2) / 2;
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}
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for (i = 0; i< 6; i++)
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ecc_bit[i] = tmp2_bit[i + 2] ^ comp2_bit[i + 2];
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for (i = 0; i < 8; i++)
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ecc_bit[i + 6] = tmp0_bit[i] ^ comp0_bit[i];
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for (i = 0; i < 8; i++)
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ecc_bit[i + 14] = tmp1_bit[i] ^ comp1_bit[i];
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ecc_bit[22] = tmp2_bit[0] ^ comp2_bit[0];
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ecc_bit[23] = tmp2_bit[1] ^ comp2_bit[1];
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for (i = 0; i < 24; i++)
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ecc_sum += ecc_bit[i];
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switch (ecc_sum) {
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case 0:
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/* Not reached because this function is not called if
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ECC values are equal */
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return 0;
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case 1:
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/* Uncorrectable error */
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DEBUG (MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
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return(-1);
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case 12:
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/* Correctable error */
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find_byte = (ecc_bit[23] << 8) +
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(ecc_bit[21] << 7) +
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(ecc_bit[19] << 6) +
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(ecc_bit[17] << 5) +
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(ecc_bit[15] << 4) +
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(ecc_bit[13] << 3) +
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(ecc_bit[11] << 2) +
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(ecc_bit[9] << 1) +
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ecc_bit[7];
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find_bit = (ecc_bit[5] << 2) + (ecc_bit[3] << 1) + ecc_bit[1];
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DEBUG (MTD_DEBUG_LEVEL0, "Correcting single bit ECC error at offset: %d, bit: %d\n", find_byte, find_bit);
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page_data[find_byte] ^= (1 << find_bit);
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return(0);
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default:
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if (is_ecc_ff) {
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if (ecc_calc[0] == 0 && ecc_calc[1] == 0 && ecc_calc[2] == 0)
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return(0);
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}
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DEBUG (MTD_DEBUG_LEVEL0, "UNCORRECTED_ERROR default\n");
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return(-1);
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}
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}
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static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
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{
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struct nand_chip *this;
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int block_count = 0, i, rc;
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this = mtd->priv;
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block_count = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1;
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for (i = 0; i < block_count; i++) {
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if (memcmp(read_ecc, calc_ecc, 3) != 0) {
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rc = nand_davinci_compare_ecc(read_ecc, calc_ecc, dat);
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if (rc < 0) {
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return(rc);
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}
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}
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read_ecc += 3;
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calc_ecc += 3;
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dat += 512;
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}
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return(0);
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}
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#endif
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static int nand_davinci_dev_ready(struct mtd_info *mtd)
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{
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emifregs emif_addr;
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emif_addr = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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return(emif_addr->NANDFSR & 0x1);
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}
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static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, int state)
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{
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while(!nand_davinci_dev_ready(mtd)) {;}
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*NAND_CE0CLE = NAND_STATUS;
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return(*NAND_CE0DATA);
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}
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static void nand_flash_init(void)
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{
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u_int32_t acfg1 = 0x3ffffffc;
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u_int32_t acfg2 = 0x3ffffffc;
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u_int32_t acfg3 = 0x3ffffffc;
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u_int32_t acfg4 = 0x3ffffffc;
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emifregs emif_regs;
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/*------------------------------------------------------------------*
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* NAND FLASH CHIP TIMEOUT @ 459 MHz *
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* *
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* AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz *
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* AEMIF.CLK period = 1/76.5 MHz = 13.1 ns *
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* *
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*------------------------------------------------------------------*/
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acfg1 = 0
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| (0 << 31 ) /* selectStrobe */
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| (0 << 30 ) /* extWait */
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| (1 << 26 ) /* writeSetup 10 ns */
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| (3 << 20 ) /* writeStrobe 40 ns */
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| (1 << 17 ) /* writeHold 10 ns */
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| (1 << 13 ) /* readSetup 10 ns */
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| (5 << 7 ) /* readStrobe 60 ns */
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| (1 << 4 ) /* readHold 10 ns */
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| (3 << 2 ) /* turnAround ?? ns */
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| (0 << 0 ) /* asyncSize 8-bit bus */
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;
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emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE;
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emif_regs->AWCCR |= 0x10000000;
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emif_regs->AB1CR = acfg1; /* 0x08244128 */;
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emif_regs->AB2CR = acfg2;
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emif_regs->AB3CR = acfg3;
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emif_regs->AB4CR = acfg4;
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emif_regs->NANDFCR = 0x00000101;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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nand->IO_ADDR_R = (void __iomem *)NAND_CE0DATA;
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nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
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nand->chip_delay = 0;
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nand->select_chip = nand_davinci_select_chip;
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#ifdef CFG_NAND_USE_FLASH_BBT
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nand->options = NAND_USE_FLASH_BBT;
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#endif
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#ifdef CFG_NAND_HW_ECC
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#ifdef CFG_NAND_LARGEPAGE
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nand->eccmode = NAND_ECC_HW12_2048;
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#elif defined(CFG_NAND_SMALLPAGE)
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nand->eccmode = NAND_ECC_HW3_512;
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#else
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#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
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#endif
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nand->autooob = &davinci_nand_oobinfo;
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nand->calculate_ecc = nand_davinci_calculate_ecc;
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nand->correct_data = nand_davinci_correct_data;
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nand->enable_hwecc = nand_davinci_enable_hwecc;
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#else
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nand->eccmode = NAND_ECC_SOFT;
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#endif
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/* Set address of hardware control function */
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nand->hwcontrol = nand_davinci_hwcontrol;
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nand->dev_ready = nand_davinci_dev_ready;
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nand->waitfunc = nand_davinci_waitfunc;
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nand_flash_init();
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return(0);
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}
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#else
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#error "U-Boot legacy NAND support not available for DaVinci chips"
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#endif
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#endif /* CFG_USE_NAND */
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