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The GICv3 RM requires "The first 1KB of memory for the LPI Pending tables must contain only zeros on initial allocation, and this must be visible to the Redistributors, or else the effect is UNPREDICTABLE". And as the following statement, we here clear the whole Pending tables instead of the first 1KB. "An LPI Pending table that contains only zeros, including in the first 1KB, indicates that there are no pending LPIs. The first 1KB of the LPI Pending table is IMPLEMENTATION DEFINED. However, if the first 1KB of the LPI Pending table and the rest of the table contain only zeros, this must indicate that there are no pending LPIs." And there isn't any pending LPI under U-Boot, so it's unnecessary to load the contents of the Pending table during the enablement, then set the GICR_PENDBASER.PTZ flag. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> # NXP LS1028A Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com> |
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.. | ||
cpu | ||
dts | ||
include | ||
lib | ||
mach-aspeed | ||
mach-at91 | ||
mach-bcm283x | ||
mach-bcmstb | ||
mach-cortina | ||
mach-davinci | ||
mach-exynos | ||
mach-highbank | ||
mach-imx | ||
mach-integrator | ||
mach-ipq40xx | ||
mach-k3 | ||
mach-keystone | ||
mach-kirkwood | ||
mach-lpc32xx | ||
mach-mediatek | ||
mach-meson | ||
mach-mvebu | ||
mach-nexell | ||
mach-octeontx | ||
mach-octeontx2 | ||
mach-omap2 | ||
mach-orion5x | ||
mach-owl | ||
mach-qemu | ||
mach-rmobile | ||
mach-rockchip | ||
mach-s5pc1xx | ||
mach-snapdragon | ||
mach-socfpga | ||
mach-sti | ||
mach-stm32 | ||
mach-stm32mp | ||
mach-sunxi | ||
mach-tegra | ||
mach-u8500 | ||
mach-uniphier | ||
mach-versal | ||
mach-versatile | ||
mach-zynq | ||
mach-zynqmp | ||
mach-zynqmp-r5 | ||
thumb1/include/asm/proc-armv | ||
config.mk | ||
Kconfig | ||
Kconfig.debug | ||
Makefile |