Priyanka Jain e809e74799 armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support ... The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Santan Kumar <santan.kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2017-05-23 09:40:23 -07:00
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clock.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
config.h	armv8: ls1043a: Drop macro CONFIG_LS1043A	2017-04-17 09:03:30 -07:00
cpu.h	armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support	2017-05-23 09:40:23 -07:00
fdt.h	armv8/layerscape: remove unnecessary function declares	2017-01-18 09:24:51 -08:00
fsl_serdes.h	armv8: ls2080a: Drop macro CONFIG_LS2080A	2017-04-17 09:03:30 -07:00
immap_lsch2.h	armv8/ls1043a: fixup GIC offset for ls1043a rev1	2017-01-18 09:29:21 -08:00
immap_lsch3.h	board: freescale: ls2080ardb: Enable SD interface for RevF board	2017-05-23 09:12:26 -07:00
imx-regs.h	serial: lpuart: restructure lpuart driver	2017-03-17 09:27:08 +01:00
mmu.h	armv8: layerscape: Update early MMU for DDR after initialization	2017-03-14 08:44:03 -07:00
mp.h	arm: psci: make psci usable on single core socs	2017-04-24 09:07:12 -07:00
ns_access.h	fsl: csu: add an API to set R/W permission to PCIe	2016-09-14 14:07:08 -07:00
ppa.h	fsl-layerscape/ppa: cleanup ppa.h	2017-03-28 08:59:47 -07:00
soc.h	armv8: fsl-layerscape: Add NXP LS2081A, LS2041A SoC support	2017-05-23 09:40:23 -07:00
speed.h	armv8/fsl_lsch3: Change arch to fsl-layerscape	2015-10-29 10:34:00 -07:00
stream_id_lsch2.h	arvm8: pcie-layerscape: Define stream-ids for Layerscape Chassis-2	2017-03-28 10:47:16 -07:00
stream_id_lsch3.h	armv8: fsl-lsch3: Rewrite comment for stream IDs	2017-03-28 10:44:47 -07:00