u-boot/arch/riscv/cpu/jh7110/Kconfig
Minda Chen eca2d41c68 riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2023-08-10 10:58:01 +08:00

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# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2022 StarFive Technology Co., Ltd.
config STARFIVE_JH7110
bool
select ARCH_EARLY_INIT_R
select CLK_JH7110
select CPU
select CPU_RISCV
select RAM
select RESET_JH7110
select SUPPORT_SPL
select SPL_RAM if SPL
select SPL_STARFIVE_DDR
select SYS_CACHE_SHIFT_6
select PINCTRL_STARFIVE_JH7110
imply MMC
imply MMC_BROKEN_CD
imply MMC_SPI
imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
imply SIFIVE_CACHE
imply SIFIVE_CCACHE
imply SMP
imply SPI
imply SPL_CPU
imply SPL_LOAD_FIT
imply SPL_OPENSBI
imply SPL_RISCV_ACLINT