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3 commits

Author SHA1 Message Date
Minda Chen
eca2d41c68 riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE 
Some device driver need SYS_CACHELINE_SIZE macro. Add StarFive
SYS_CACHE_SHIFT_6 to enable it.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
 2023-08-10 10:58:01 +08:00
Bin Meng
9675d92027 riscv: Rename SiFive CLINT to RISC-V ALINT 
As the RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V
ALINT in the source tree to be future-proof.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
 2023-07-12 13:21:40 +08:00
Yanhong Wang
2f5fad0b0d riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC 
Add Kconfig to select the basic functions for StarFive JH7110 SoC.

Signed-off-by: Yanhong Wang <yanhong.wang@starfivetech.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
 2023-04-20 16:08:44 +08:00