Shengyu Qu 6419f8e9fd riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation ... Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove existing Starfive JH7110's L2 LIM clean code, since existing code has following issues: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing "board_init_f_init_reserve", while other harts are in the middle of zeroing L2 LIM. (data-race) Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2023-08-10 10:58:12 +08:00
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cpu.c	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
dram.c	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
Kconfig	riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE	2023-08-10 10:58:01 +08:00
Makefile	riscv: cpu: jh7110: Add support for jh7110 SoC	2023-04-20 16:08:44 +08:00
spl.c	riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation	2023-08-10 10:58:12 +08:00