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2564fce7ee
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB maintenance operations are done. As we do those things still in start.S, we need to move the SMPEN bit setting there, too. This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR very early in start.S, and moves sunxi boards over to use that instead of the custom code we had in our board.c file (where it was called technically too late). In practice we got away with this so far, because at this point all the other cores were still in reset, so any broadcasting would have been ignored anyway. But it is architecturally cleaner to do it early, and we move a core specific piece of code out of board.c. This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few years back, and moves the respective logic into the new Kconfig entry. Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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| .. | ||
| cpu | ||
| dts | ||
| include | ||
| lib | ||
| mach-apple | ||
| mach-aspeed | ||
| mach-at91 | ||
| mach-bcm283x | ||
| mach-bcmstb | ||
| mach-cortina | ||
| mach-davinci | ||
| mach-exynos | ||
| mach-highbank | ||
| mach-imx | ||
| mach-integrator | ||
| mach-ipq40xx | ||
| mach-k3 | ||
| mach-keystone | ||
| mach-kirkwood | ||
| mach-lpc32xx | ||
| mach-mediatek | ||
| mach-meson | ||
| mach-mvebu | ||
| mach-nexell | ||
| mach-octeontx | ||
| mach-octeontx2 | ||
| mach-omap2 | ||
| mach-orion5x | ||
| mach-owl | ||
| mach-qemu | ||
| mach-rmobile | ||
| mach-rockchip | ||
| mach-s5pc1xx | ||
| mach-snapdragon | ||
| mach-socfpga | ||
| mach-sti | ||
| mach-stm32 | ||
| mach-stm32mp | ||
| mach-sunxi | ||
| mach-tegra | ||
| mach-u8500 | ||
| mach-uniphier | ||
| mach-versal | ||
| mach-versatile | ||
| mach-zynq | ||
| mach-zynqmp | ||
| mach-zynqmp-r5 | ||
| thumb1/include/asm/proc-armv | ||
| config.mk | ||
| Kconfig | ||
| Kconfig.debug | ||
| Makefile | ||