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9675d92027
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
55 lines
939 B
Text
55 lines
939 B
Text
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2020-2021 SiFive, Inc
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# Pragnesh Patel <pragnesh.patel@sifive.com>
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config SIFIVE_FU740
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bool
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select ARCH_EARLY_INIT_R
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select RAM
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select SPL_RAM if SPL
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imply CPU
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imply CPU_RISCV
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply SPL_RISCV_ACLINT
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imply CMD_CPU
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imply SPL_CPU
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imply SPL_OPENSBI
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imply SPL_LOAD_FIT
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imply SMP
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imply CLK_SIFIVE
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imply CLK_SIFIVE_PRCI
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imply SIFIVE_CACHE
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imply SIFIVE_CCACHE
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imply SIFIVE_SERIAL
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imply MACB
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imply MII
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imply SPI
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imply SPI_SIFIVE
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imply MMC
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imply MMC_SPI
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imply MMC_BROKEN_CD
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imply CMD_MMC
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imply DM_GPIO
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imply SIFIVE_GPIO
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imply CMD_GPIO
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imply MISC
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imply SIFIVE_OTP
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imply DM_PWM
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imply PWM_SIFIVE
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imply DM_I2C
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imply SYS_I2C_OCORES
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imply SPL_I2C
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if ENV_IS_IN_SPI_FLASH
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config ENV_OFFSET
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default 0x505000
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config ENV_SIZE
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default 0x20000
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config ENV_SECT_SIZE
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default 0x10000
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endif # ENV_IS_IN_SPI_FLASH
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