Bin Meng 9675d92027 riscv: Rename SiFive CLINT to RISC-V ALINT ... As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>		2023-07-12 13:21:40 +08:00
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andesv5	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
fu540	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
fu740	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
generic	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
jh7110	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
cpu.c	dm: Emit the arch_cpu_init_dm() even only before relocation	2023-05-11 10:25:29 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: spl: Remove relocation sections	2023-04-20 20:45:08 +08:00
u-boot-spl.lds	riscv: Update alignment for some sections in linker scripts	2023-04-20 20:45:08 +08:00
u-boot.lds	riscv: Fix alignment of RELA sections in the linker scripts	2023-06-27 10:09:51 +08:00