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u-boot/board/freescale/p1_p2_rdb_pc
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Xu Jiucheng 545c12cf9a powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PC 
When P1021RDB-PC reboot system, the board will hung at uboot DDR
configuration. For P1021RDB-PC DDR reset pin is multiplex with
QE, so uboot will reserve this pin for QE and skip DDR reset.
Other platforms without QE will do this reset. This patch adds
a slight code to reset DDR chip by QE CE_PB8 pin for NAND and
NOR FLASH boot. For booting from SPI FALSH and SD card, it
seems possible to use the rom on chip to write to the GPIO
pins before configuring the DDR.

Signed-off-by: Xu Jiucheng <B37781@freescale.com>
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
2013-05-02 16:57:34 -05:00
..
ddr.c powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot 2012-11-26 15:41:27 -06:00
law.c powerpc/mpc85xx/p1_p2_rdb_pc: clean up memory map 2012-11-26 15:41:26 -06:00
Makefile powerpc/mpc85xx/p1_p2_rdb_pc: new SPL support 2012-11-26 15:41:25 -06:00
p1_p2_rdb_pc.c powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PC 2013-05-02 16:57:34 -05:00
README doc: cleanup - move board READMEs into respective board directories 2012-07-29 15:42:02 +02:00
spl_minimal.c powerpc/p1_p2_rdb_pc: Add a pin to reset the DDR chip for P1021RDB-PC 2013-05-02 16:57:34 -05:00
tlb.c powerpc/mpc85xx/p2020rdb-pca: Use L2 SRAM for SPL boot 2012-11-26 15:41:27 -06:00

README 

Overview
--------
P1_P2_RDB_PC represents a set of boards including
    P1020MSBG-PC
    P1020RDB-PC
    P1020UTM-PC
    P1021RDB-PC
    P1024RDB
    P1025RDB
    P2020RDB-PC

They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC
has 64-bit DDR. All others have 32-bit DDR.

Key features on these boards include:
    * DDR3
    * NOR flash
    * NAND flash (on RDB's only)
    * SPI flash (on RDB's only)
    * SDHC/MMC card slot
    * VSC7385 Ethernet switch (on P1020MBG, P1020RDB, & P1021RDB)
    * PCIE slot and mini-PCIE slots

As these boards use soldered DDR chips not regular DIMMs, an on-board EEPROM
is used to store SPD data. In case of absent or corrupted SPD, falling back
to timing data embedded in the source code will be used. Raw timing data is
extracted from DDR chip datasheet. Different speeds of DDR are supported with
this approach. ODT option is forced to fit this set of boards, again because
they don't have regular DIMMs.

CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS is defined as 5ms to meet specification
for writing timing.

VSC firmware Address is defined by default in config file for eTSEC1.

SD width is based off DIP switch. DIP switch is detected on the
board by reading i2c bus and setting the appropriate mux values.

Some boards have QE module in the silicon (P1021 and P1025). QE and eLBC have
pins multiplexing. QE function needs to be disabled to access Nor Flash and
CPLD. QE-UEC and QE-UART can be enabled for linux kernel by setting "qe"
in hwconfig. In addition, QE-UEC and QE-TDM also have pins multiplexing, to
enable QE-TDM for linux kernel, set "qe;tdm" in hwconfig. Syntax is as below

'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.