Andrey Zhizhikin 1289ff7bd7 imx8m: lock id_swap_bypass bit in tzc380 enable ... According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in order to avoid AXI bus errors when GPU is enabled on the platform. TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable derivatives, but is missing a lock settings to be applied. Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have it implemented. Since we're here, provide also names to bits from TRM instead of using BIT() macro in the code. Fixes: deca6cfbf5 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors") Fixes: a07c718129 ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Peng Fan <peng.fan@nxp.com>		2022-02-05 15:49:01 +01:00
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clock.h	arm: imx8mq: Add USB clock init function	2021-07-17 13:12:23 +02:00
clock_imx8mm.h	common: Drop linux/bitops.h from common header	2020-05-18 21:19:23 -04:00
clock_imx8mq.h	imx8mq: fix SSCG_PLL_REFCLK_SEL_x	2020-09-17 14:40:10 +02:00
crm_regs.h
ddr.h	drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue	2020-07-14 15:23:46 +08:00
gpio.h
imx-regs.h	imx8m: lock id_swap_bypass bit in tzc380 enable	2022-02-05 15:49:01 +01:00
imx8mm_pins.h	imx8m: add pin header for i.MX8MM	2019-10-08 16:36:36 +02:00
imx8mn_pins.h	imx8mn: add pin header	2019-11-05 10:27:18 +01:00
imx8mp_pins.h	imx: imx8mp: add pin header file	2020-01-08 13:20:08 +01:00
imx8mq_pins.h
lpddr4_define.h	imx: imx8m: add lpddr4 header file	2019-01-01 14:12:18 +01:00
power-domain.h	dm: treewide: Rename ..._platdata variables to just ..._plat	2020-12-13 16:51:09 -07:00
sys_proto.h