mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 19:10:13 +00:00
1289ff7bd7
According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in order to avoid AXI bus errors when GPU is enabled on the platform. TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable derivatives, but is missing a lock settings to be applied. Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have it implemented. Since we're here, provide also names to bits from TRM instead of using BIT() macro in the code. Fixes:deca6cfbf5
("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors") Fixes:a07c718129
("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors") Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Peng Fan <peng.fan@nxp.com>
519 lines
10 KiB
C
519 lines
10 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017 NXP
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*/
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#ifndef __ASM_ARCH_IMX8M_REGS_H__
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#define __ASM_ARCH_IMX8M_REGS_H__
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#define ARCH_MXC
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#include <asm/mach-imx/regs-lcdif.h>
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#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
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#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
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#define M4_BOOTROM_BASE_ADDR 0x007E0000
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#define GPIO1_BASE_ADDR 0X30200000
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#define GPIO2_BASE_ADDR 0x30210000
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#define GPIO3_BASE_ADDR 0x30220000
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#define GPIO4_BASE_ADDR 0x30230000
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#define GPIO5_BASE_ADDR 0x30240000
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#define WDOG1_BASE_ADDR 0x30280000
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#define WDOG2_BASE_ADDR 0x30290000
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#define WDOG3_BASE_ADDR 0x302A0000
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#define IOMUXC_BASE_ADDR 0x30330000
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#define IOMUXC_GPR_BASE_ADDR 0x30340000
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#define OCOTP_BASE_ADDR 0x30350000
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#define ANATOP_BASE_ADDR 0x30360000
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#define CCM_BASE_ADDR 0x30380000
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#define SRC_BASE_ADDR 0x30390000
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#define GPC_BASE_ADDR 0x303A0000
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#define SYSCNT_RD_BASE_ADDR 0x306A0000
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#define SYSCNT_CMP_BASE_ADDR 0x306B0000
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#define SYSCNT_CTRL_BASE_ADDR 0x306C0000
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#define UART1_BASE_ADDR 0x30860000
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#define UART3_BASE_ADDR 0x30880000
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#define UART2_BASE_ADDR 0x30890000
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#define I2C1_BASE_ADDR 0x30A20000
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#define I2C2_BASE_ADDR 0x30A30000
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#define I2C3_BASE_ADDR 0x30A40000
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#define I2C4_BASE_ADDR 0x30A50000
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#define UART4_BASE_ADDR 0x30A60000
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#define USDHC1_BASE_ADDR 0x30B40000
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#define USDHC2_BASE_ADDR 0x30B50000
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#ifdef CONFIG_IMX8MM
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#define USDHC3_BASE_ADDR 0x30B60000
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#endif
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#define TZASC_BASE_ADDR 0x32F80000
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#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \
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0x30320000 : 0x32e00000
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#define SRC_IPS_BASE_ADDR 0x30390000
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#define SRC_DDRC_RCR_ADDR 0x30391000
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#define SRC_DDRC2_RCR_ADDR 0x30391004
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#define DDRC_DDR_SS_GPR0 0x3d000000
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#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
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#define DDR_CSD1_BASE_ADDR 0x40000000
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#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x70000
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#define FEC_QUIRK_ENET_MAC
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#define CAAM_ARB_BASE_ADDR (0x00100000)
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#define CAAM_ARB_END_ADDR (0x00107FFF)
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#define CAAM_IPS_BASE_ADDR (0x30900000)
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#define CONFIG_SYS_FSL_SEC_OFFSET (0)
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#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
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CONFIG_SYS_FSL_SEC_OFFSET)
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#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
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#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
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CONFIG_SYS_FSL_JR0_OFFSET)
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#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
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#if !defined(__ASSEMBLY__)
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#include <asm/types.h>
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#include <linux/bitops.h>
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#include <stdbool.h>
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#define GPR_TZASC_EN BIT(0)
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#define GPR_TZASC_ID_SWAP_BYPASS BIT(1)
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#define GPR_TZASC_EN_LOCK BIT(16)
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#define GPR_TZASC_ID_SWAP_BYPASS_LOCK BIT(17)
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#define SRC_SCR_M4_ENABLE_OFFSET 3
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#define SRC_SCR_M4_ENABLE_MASK BIT(3)
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#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET 0
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#define SRC_SCR_M4C_NON_SCLR_RST_MASK BIT(0)
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#define SRC_DDR1_ENABLE_MASK 0x8F000000UL
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#define SRC_DDR2_ENABLE_MASK 0x8F000000UL
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#define SRC_DDR1_RCR_PHY_PWROKIN_N_MASK BIT(3)
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#define SRC_DDR1_RCR_PHY_RESET_MASK BIT(2)
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#define SRC_DDR1_RCR_CORE_RESET_N_MASK BIT(1)
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#define SRC_DDR1_RCR_PRESET_N_MASK BIT(0)
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struct iomuxc_gpr_base_regs {
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u32 gpr[47];
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};
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struct ocotp_regs {
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u32 ctrl;
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u32 ctrl_set;
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u32 ctrl_clr;
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u32 ctrl_tog;
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u32 timing;
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u32 rsvd0[3];
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u32 data;
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u32 rsvd1[3];
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u32 read_ctrl;
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u32 rsvd2[3];
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u32 read_fuse_data;
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u32 rsvd3[3];
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u32 sw_sticky;
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u32 rsvd4[3];
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u32 scs;
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u32 scs_set;
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u32 scs_clr;
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u32 scs_tog;
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u32 crc_addr;
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u32 rsvd5[3];
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u32 crc_value;
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u32 rsvd6[3];
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u32 version;
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u32 rsvd7[0xdb];
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/* fuse banks */
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struct fuse_bank {
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u32 fuse_regs[0x10];
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} bank[0];
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};
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#ifdef CONFIG_IMX8MP
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struct fuse_bank0_regs {
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u32 lock;
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u32 rsvd0[7];
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u32 uid_low;
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u32 rsvd1[3];
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u32 uid_high;
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u32 rsvd2[3];
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};
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#else
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struct fuse_bank0_regs {
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u32 lock;
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u32 rsvd0[3];
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u32 uid_low;
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u32 rsvd1[3];
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u32 uid_high;
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u32 rsvd2[7];
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};
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#endif
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struct fuse_bank1_regs {
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u32 tester3;
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u32 rsvd0[3];
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u32 tester4;
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u32 rsvd1[3];
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u32 tester5;
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u32 rsvd2[3];
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u32 cfg0;
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u32 rsvd3[3];
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};
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struct fuse_bank3_regs {
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u32 mem_trim0;
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u32 rsvd0[3];
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u32 mem_trim1;
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u32 rsvd1[3];
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u32 mem_trim2;
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u32 rsvd2[3];
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u32 ana0;
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u32 rsvd3[3];
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};
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struct fuse_bank9_regs {
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u32 mac_addr0;
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u32 rsvd0[3];
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u32 mac_addr1;
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u32 rsvd1[11];
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};
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struct fuse_bank38_regs {
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u32 ana_trim1; /* trim0 is at 0xD70, bank 37*/
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u32 rsvd0[3];
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u32 ana_trim2;
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u32 rsvd1[3];
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u32 ana_trim3;
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u32 rsvd2[3];
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u32 ana_trim4;
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u32 rsvd3[3];
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};
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struct fuse_bank39_regs {
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u32 ana_trim5;
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u32 rsvd[15];
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};
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#ifdef CONFIG_IMX8MQ
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struct anamix_pll {
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u32 audio_pll1_cfg0;
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u32 audio_pll1_cfg1;
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u32 audio_pll2_cfg0;
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u32 audio_pll2_cfg1;
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u32 video_pll_cfg0;
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u32 video_pll_cfg1;
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u32 gpu_pll_cfg0;
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u32 gpu_pll_cfg1;
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u32 vpu_pll_cfg0;
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u32 vpu_pll_cfg1;
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u32 arm_pll_cfg0;
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u32 arm_pll_cfg1;
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u32 sys_pll1_cfg0;
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u32 sys_pll1_cfg1;
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u32 sys_pll1_cfg2;
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u32 sys_pll2_cfg0;
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u32 sys_pll2_cfg1;
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u32 sys_pll2_cfg2;
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u32 sys_pll3_cfg0;
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u32 sys_pll3_cfg1;
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u32 sys_pll3_cfg2;
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u32 video_pll2_cfg0;
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u32 video_pll2_cfg1;
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u32 video_pll2_cfg2;
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u32 dram_pll_cfg0;
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u32 dram_pll_cfg1;
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u32 dram_pll_cfg2;
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u32 digprog;
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u32 osc_misc_cfg;
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u32 pllout_monitor_cfg;
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u32 frac_pllout_div_cfg;
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u32 sscg_pllout_div_cfg;
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};
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#else
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struct anamix_pll {
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u32 audio_pll1_gnrl_ctl;
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u32 audio_pll1_fdiv_ctl0;
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u32 audio_pll1_fdiv_ctl1;
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u32 audio_pll1_sscg_ctl;
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u32 audio_pll1_mnit_ctl;
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u32 audio_pll2_gnrl_ctl;
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u32 audio_pll2_fdiv_ctl0;
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u32 audio_pll2_fdiv_ctl1;
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u32 audio_pll2_sscg_ctl;
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u32 audio_pll2_mnit_ctl;
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u32 video_pll1_gnrl_ctl;
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u32 video_pll1_fdiv_ctl0;
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u32 video_pll1_fdiv_ctl1;
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u32 video_pll1_sscg_ctl;
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u32 video_pll1_mnit_ctl;
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u32 reserved[5];
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u32 dram_pll_gnrl_ctl;
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u32 dram_pll_fdiv_ctl0;
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u32 dram_pll_fdiv_ctl1;
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u32 dram_pll_sscg_ctl;
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u32 dram_pll_mnit_ctl;
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u32 gpu_pll_gnrl_ctl;
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u32 gpu_pll_div_ctl;
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u32 gpu_pll_locked_ctl1;
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u32 gpu_pll_mnit_ctl;
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u32 vpu_pll_gnrl_ctl;
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u32 vpu_pll_div_ctl;
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u32 vpu_pll_locked_ctl1;
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u32 vpu_pll_mnit_ctl;
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u32 arm_pll_gnrl_ctl;
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u32 arm_pll_div_ctl;
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u32 arm_pll_locked_ctl1;
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u32 arm_pll_mnit_ctl;
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u32 sys_pll1_gnrl_ctl;
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u32 sys_pll1_div_ctl;
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u32 sys_pll1_locked_ctl1;
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u32 reserved2[24];
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u32 sys_pll1_mnit_ctl;
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u32 sys_pll2_gnrl_ctl;
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u32 sys_pll2_div_ctl;
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u32 sys_pll2_locked_ctl1;
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u32 sys_pll2_mnit_ctl;
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u32 sys_pll3_gnrl_ctl;
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u32 sys_pll3_div_ctl;
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u32 sys_pll3_locked_ctl1;
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u32 sys_pll3_mnit_ctl;
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u32 anamix_misc_ctl;
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u32 anamix_clk_mnit_ctl;
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u32 reserved3[437];
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u32 digprog;
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};
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#endif
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/* System Reset Controller (SRC) */
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struct src {
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u32 scr;
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u32 a53rcr;
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u32 a53rcr1;
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u32 m4rcr;
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u32 reserved1[4];
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u32 usbophy1_rcr;
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u32 usbophy2_rcr;
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u32 mipiphy_rcr;
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u32 pciephy_rcr;
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u32 hdmi_rcr;
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u32 disp_rcr;
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u32 reserved2[2];
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u32 gpu_rcr;
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u32 vpu_rcr;
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u32 pcie2_rcr;
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u32 mipiphy1_rcr;
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u32 mipiphy2_rcr;
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u32 reserved3;
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u32 sbmr1;
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u32 srsr;
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u32 reserved4[2];
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u32 sisr;
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u32 simr;
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u32 sbmr2;
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u32 gpr1;
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u32 gpr2;
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u32 gpr3;
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u32 gpr4;
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u32 gpr5;
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u32 gpr6;
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u32 gpr7;
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u32 gpr8;
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u32 gpr9;
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u32 gpr10;
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u32 reserved5[985];
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u32 ddr1_rcr;
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u32 ddr2_rcr;
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};
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#define WDOG_WDT_MASK BIT(3)
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#define WDOG_WDZST_MASK BIT(0)
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struct wdog_regs {
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u16 wcr; /* Control */
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u16 wsr; /* Service */
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u16 wrsr; /* Reset Status */
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u16 wicr; /* Interrupt Control */
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u16 wmcr; /* Miscellaneous Control */
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};
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struct bootrom_sw_info {
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u8 reserved_1;
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u8 boot_dev_instance;
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u8 boot_dev_type;
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u8 reserved_2;
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u32 core_freq;
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u32 axi_freq;
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u32 ddr_freq;
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u32 tick_freq;
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u32 reserved_3[3];
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};
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#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
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0x000009e8)
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#define ROM_SW_INFO_ADDR_A0 0x000009e8
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#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_A0 : \
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(struct bootrom_sw_info **)ROM_SW_INFO_ADDR_B0
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struct gpc_reg {
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u32 lpcr_bsc;
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u32 lpcr_ad;
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u32 lpcr_cpu1;
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u32 lpcr_cpu2;
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u32 lpcr_cpu3;
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u32 slpcr;
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u32 mst_cpu_mapping;
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u32 mmdc_cpu_mapping;
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u32 mlpcr;
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u32 pgc_ack_sel;
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u32 pgc_ack_sel_m4;
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u32 gpc_misc;
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u32 imr1_core0;
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u32 imr2_core0;
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u32 imr3_core0;
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u32 imr4_core0;
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u32 imr1_core1;
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u32 imr2_core1;
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u32 imr3_core1;
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u32 imr4_core1;
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u32 imr1_cpu1;
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u32 imr2_cpu1;
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u32 imr3_cpu1;
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u32 imr4_cpu1;
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u32 imr1_cpu3;
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u32 imr2_cpu3;
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u32 imr3_cpu3;
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u32 imr4_cpu3;
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u32 isr1_cpu0;
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u32 isr2_cpu0;
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u32 isr3_cpu0;
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u32 isr4_cpu0;
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u32 isr1_cpu1;
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u32 isr2_cpu1;
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u32 isr3_cpu1;
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u32 isr4_cpu1;
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u32 isr1_cpu2;
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u32 isr2_cpu2;
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u32 isr3_cpu2;
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u32 isr4_cpu2;
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u32 isr1_cpu3;
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u32 isr2_cpu3;
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u32 isr3_cpu3;
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u32 isr4_cpu3;
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u32 slt0_cfg;
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u32 slt1_cfg;
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u32 slt2_cfg;
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u32 slt3_cfg;
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u32 slt4_cfg;
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u32 slt5_cfg;
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u32 slt6_cfg;
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u32 slt7_cfg;
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u32 slt8_cfg;
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u32 slt9_cfg;
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u32 slt10_cfg;
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u32 slt11_cfg;
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u32 slt12_cfg;
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u32 slt13_cfg;
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u32 slt14_cfg;
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u32 pgc_cpu_0_1_mapping;
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u32 cpu_pgc_up_trg;
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u32 mix_pgc_up_trg;
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u32 pu_pgc_up_trg;
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u32 cpu_pgc_dn_trg;
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u32 mix_pgc_dn_trg;
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u32 pu_pgc_dn_trg;
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u32 lpcr_bsc2;
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u32 pgc_cpu_2_3_mapping;
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u32 lps_cpu0;
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u32 lps_cpu1;
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u32 lps_cpu2;
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u32 lps_cpu3;
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u32 gpc_gpr;
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u32 gtor;
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u32 debug_addr1;
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u32 debug_addr2;
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u32 cpu_pgc_up_status1;
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u32 mix_pgc_up_status0;
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u32 mix_pgc_up_status1;
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u32 mix_pgc_up_status2;
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u32 m4_mix_pgc_up_status0;
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u32 m4_mix_pgc_up_status1;
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u32 m4_mix_pgc_up_status2;
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u32 pu_pgc_up_status0;
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u32 pu_pgc_up_status1;
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u32 pu_pgc_up_status2;
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u32 m4_pu_pgc_up_status0;
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u32 m4_pu_pgc_up_status1;
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u32 m4_pu_pgc_up_status2;
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u32 a53_lp_io_0;
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u32 a53_lp_io_1;
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u32 a53_lp_io_2;
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u32 cpu_pgc_dn_status1;
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u32 mix_pgc_dn_status0;
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u32 mix_pgc_dn_status1;
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|
u32 mix_pgc_dn_status2;
|
|
u32 m4_mix_pgc_dn_status0;
|
|
u32 m4_mix_pgc_dn_status1;
|
|
u32 m4_mix_pgc_dn_status2;
|
|
u32 pu_pgc_dn_status0;
|
|
u32 pu_pgc_dn_status1;
|
|
u32 pu_pgc_dn_status2;
|
|
u32 m4_pu_pgc_dn_status0;
|
|
u32 m4_pu_pgc_dn_status1;
|
|
u32 m4_pu_pgc_dn_status2;
|
|
u32 res[3];
|
|
u32 mix_pdn_flg;
|
|
u32 pu_pdn_flg;
|
|
u32 m4_mix_pdn_flg;
|
|
u32 m4_pu_pdn_flg;
|
|
u32 imr1_core2;
|
|
u32 imr2_core2;
|
|
u32 imr3_core2;
|
|
u32 imr4_core2;
|
|
u32 imr1_core3;
|
|
u32 imr2_core3;
|
|
u32 imr3_core3;
|
|
u32 imr4_core3;
|
|
u32 pgc_ack_sel_pu;
|
|
u32 pgc_ack_sel_m4_pu;
|
|
u32 slt15_cfg;
|
|
u32 slt16_cfg;
|
|
u32 slt17_cfg;
|
|
u32 slt18_cfg;
|
|
u32 slt19_cfg;
|
|
u32 gpc_pu_pwrhsk;
|
|
u32 slt0_cfg_pu;
|
|
u32 slt1_cfg_pu;
|
|
u32 slt2_cfg_pu;
|
|
u32 slt3_cfg_pu;
|
|
u32 slt4_cfg_pu;
|
|
u32 slt5_cfg_pu;
|
|
u32 slt6_cfg_pu;
|
|
u32 slt7_cfg_pu;
|
|
u32 slt8_cfg_pu;
|
|
u32 slt9_cfg_pu;
|
|
u32 slt10_cfg_pu;
|
|
u32 slt11_cfg_pu;
|
|
u32 slt12_cfg_pu;
|
|
u32 slt13_cfg_pu;
|
|
u32 slt14_cfg_pu;
|
|
u32 slt15_cfg_pu;
|
|
u32 slt16_cfg_pu;
|
|
u32 slt17_cfg_pu;
|
|
u32 slt18_cfg_pu;
|
|
u32 slt19_cfg_pu;
|
|
};
|
|
|
|
struct pgc_reg {
|
|
u32 pgcr;
|
|
u32 pgpupscr;
|
|
u32 pgpdnscr;
|
|
u32 pgsr;
|
|
u32 pgauxsw;
|
|
u32 pgdr;
|
|
};
|
|
#endif
|
|
#endif
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