Bin Meng 4a3efd71cd riscv: Fix alignment of RELA sections in the linker scripts ... In current linker script both .efi_runtime_rel and .rela.dyn sections are of RELA type whose entry size is either 12 (RV32) or 24 (RV64). These two are arranged as a continuous region on purpose so that the prelink-riscv executable can fix up the PIE addresses in one loop. However there is an 'ALIGN(8)' between these 2 sections which might cause a gap to be inserted between these 2 sections to satisfy the alignment requirement on RV32. This would break the assumption of the prelink process and generate an unbootable image. Fixes: 9a6569a043 ("riscv: Update alignment for some sections in linker scripts") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>		2023-06-27 10:09:51 +08:00
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andesv5	riscv: Rename Andes cpu and board names	2023-02-17 19:07:48 +08:00
fu540	board_f: Fix types for board_get_usable_ram_top()	2022-09-23 15:12:42 -04:00
fu740	board_f: Fix types for board_get_usable_ram_top()	2022-09-23 15:12:42 -04:00
generic	board_f: Fix types for board_get_usable_ram_top()	2022-09-23 15:12:42 -04:00
jh7110	riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC	2023-04-20 16:08:44 +08:00
cpu.c	dm: Emit the arch_cpu_init_dm() even only before relocation	2023-05-11 10:25:29 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: spl: Remove relocation sections	2023-04-20 20:45:08 +08:00
u-boot-spl.lds	riscv: Update alignment for some sections in linker scripts	2023-04-20 20:45:08 +08:00
u-boot.lds	riscv: Fix alignment of RELA sections in the linker scripts	2023-06-27 10:09:51 +08:00