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08806a6e52
Early revisions of the R-Car V4M Series Hardware User’s Manual
contained an incorrect formula for the CPU core clocks:
ZCnφ = (PLL2VCO x 1/2) x mult/32
Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the
parent clock.
In Rev.0.70 of the documentation, the formula was corrected to:
ZCnφ = (PLL2VCO x 1/4) x mult/32
As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2,
the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get
rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the
invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4
(and Gen3) SoCs.
Ported from Linux commit
92850bed9d4d ("clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks")
Reported-by: Vinh Nguyen <vinh.nguyen.xz@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/0d2789cac2bf306145fe0bbf269c2da5942bb68f.1728377724.git.geert+renesas@glider.be
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
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| .. | ||
| clk-rcar-gen2.c | ||
| clk-rcar-gen3.c | ||
| Kconfig | ||
| Makefile | ||
| r8a774a1-cpg-mssr.c | ||
| r8a774b1-cpg-mssr.c | ||
| r8a774c0-cpg-mssr.c | ||
| r8a774e1-cpg-mssr.c | ||
| r8a779a0-cpg-mssr.c | ||
| r8a779f0-cpg-mssr.c | ||
| r8a779g0-cpg-mssr.c | ||
| r8a779h0-cpg-mssr.c | ||
| r8a7790-cpg-mssr.c | ||
| r8a7791-cpg-mssr.c | ||
| r8a7792-cpg-mssr.c | ||
| r8a7794-cpg-mssr.c | ||
| r8a7795-cpg-mssr.c | ||
| r8a7796-cpg-mssr.c | ||
| r8a77965-cpg-mssr.c | ||
| r8a77970-cpg-mssr.c | ||
| r8a77980-cpg-mssr.c | ||
| r8a77990-cpg-mssr.c | ||
| r8a77995-cpg-mssr.c | ||
| r9a06g032-clocks.c | ||
| r9a07g044-cpg.c | ||
| rcar-cpg-lib.c | ||
| rcar-cpg-lib.h | ||
| rcar-gen2-cpg.h | ||
| rcar-gen3-cpg.h | ||
| renesas-cpg-mssr.c | ||
| renesas-cpg-mssr.h | ||
| rzg2l-cpg.c | ||
| rzg2l-cpg.h | ||