128MB seems to be the smallest possible value for the memory size
for on PCIe port. With this change now the BAR's of the PCIe cards
are accessible under U-Boot.
One big note: This only works for PCIe port 0 & 1. For port 2 this
currently doesn't work, since the base address is now 0xc0000000
(0xb0000000 + 2 * 0x08000000), and this is already occupied by
CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean
to change the base addresses completely and this change would have
too much impact right now.
This patch adds debug output to the 4xx pcie driver too.
Signed-off-by: Stefan Roese <sr@denx.de>
These files were introduced with the IBM 405GP but are currently used on all
4xx PPC platforms. So the name doesn't match the content anymore. This patch
renames the files to 4xx_pci.c/h.
Signed-off-by: Stefan Roese <sr@denx.de>
(3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access
the SDR registers of the PCIe ports. This makes the overall design
clearer, since it removed a lot of switch statements which are not
needed anymore.
Also, the functions ppc4xx_init_pcie_rootport() and
ppc4xx_init_pcie_entport() are merged into a single function
ppc4xx_init_pcie_port(), since most of the code was duplicated.
This makes maintainance and porting to other 4xx platforms
easier.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(2) This patch renames the functions from 440spe_ to 4xx_ with a
little additional cleanup
Signed-off-by: Stefan Roese <sr@denx.de>
This patch is the first patch of a series to make the 440SPe PCIe code
usable on different 4xx PPC platforms. In preperation for the new 405EX
which is also equipped with PCIe interfaces.
(1) This patch renames the files from 440spe_pcie to 4xx_pcie
Signed-off-by: Stefan Roese <sr@denx.de>
With this patch PSC3 is configured as UART. This is done, because if
the pins of PSC3 are not configured at all (-> all pins are GPI),
due to crosstalk, spurious characters may be send over the RX232_2_TXD
signal line.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Some commands for the STK52xx base board try to access the SM501 grafic
controller. But the TQM5200S has no grafic controller (only the TQM5200
and the TQM5200B have). This patch deactivates the commands accessing
the SM501 for the TQM5200S.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
Patch 16e23c3f removed PCSRBAR allocation. But passing zero windows
to pciauto_setup_device has the side effect of not getting
COMMAND_MEMORY set.
Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
The pxa255_idp being an old unmaintained board showed several issues:
1. CONFIG_INIT_CRITICAL was still defined.
2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined.
3. Symbol flash_addr was undeclared.
4. The boards lowlevel_init function was still called memsetup.
5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000.
6. Using -march=armv5 instead of -march=armv5te resulted in lots of
'target CPU does not support interworking' warnings on recent compilers.
7. The PXA's serial driver redefined FFUART, BTUART and STUART used as
indexes rather than the register definitions from the pxa-regs header
file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to
avoid any ambiguities.
8. There were several redefinition warnings concerning ICMR, OSMR3,
OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file.
9. The board configuration file was rather outdated.
10. The part header file defined the vendor, product and revision arrays
as unsigned chars instead of just chars in the block_dev_desc_t
structure.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
New board has faster oscillator and a different Flash chip. This affects:
- CFG_MPC5XXX_CLKIN
- SDRAM timings
- Flash CS configuration (timings)
- Flash sector size, and thus MTD partition layout
- malloc() arena size (due to bigger Flash sectors)
- smaller memory test range (due to bigger malloc() arena)
This patch also enables more extensive memory testing via "mtest".
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Per AN3221 (MPC5200B SDRAM Initialization and Configuration), the SDelay
register must be written a value of 0x00000004 as the first step of the
SDRAM contorller configuration.
Signed-off-by: Bartlomiej Sieka <tur@semihalf.com>
Fixed typo in ne2000.h, thinko re n2k_inb() usage, don't try
to do anything in eth_stop() if eth_init() was not called.
Simplified RX path in order to avoid timeouts on really really
fast NE2000 cards (read: qemu with internal tftp), NetLoop() is
clever enough to cope with 1 packet per eth_rx().
Signed-off-by: Vlad Lungu <vlad@comsys.ro>
Add MPC8360EMDS_ATM_config and MPC832XEMDS_ATM_config into
Makfile and MAKEALL
Signed-off-by: Tony Li <tony.li@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
As a direct correlation exists between DDR DIMM slots
and SPD EEPROM addresses used to configure them, use
the individually defined SPD_EEPROM_ADDRESS* values to
determine if a DDR DIMM slot should have its SPD
configuration read or not.
Effectively, this now allows for 1 or 2 DIMM slots
per memory controller.
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Some USB keys need to be switched off before loading the kernel
otherwise they can remain in an undefined status which prevents them
to be correctly recognized by the kernel.
Signed-off-by: Rodolfo Giometti <giometti@linux.it>
The I2C bootstrap values that can be setup via the "bootstrap" command,
were setup incorrect regarding the generation of the internal sync PCI
clock. The values for PLB clock == 133MHz were slighly incorrect and the
values for PLB clock == 166MHz were totally incorrect. This could
lead to a hangup upon booting while PCI configuration scan.
This patch fixes this issue and configures valid PCI divisor values
for the sync PCI clock, with respect to the provided external async
PCI frequency.
Here the values of the formula in the chapter 14.2 "PCI clocking"
from the 440EPx users manual:
AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz
33MHz async PCI frequency:
PLB = 133:
=> 32 <= 44.3 <= 65 (div = 3)
PLB = 166:
=> 32 <= 55.3 <= 65 (div = 3)
66MHz async PCI frequency:
PLB = 133:
=> 65 <= 66.5 <= 132 (div = 2)
PLB = 166:
=> 65 <= 83 <= 132 (div = 2)
Signed-off-by: Stefan Roese <sr@denx.de>
The BCSR status bit for the 66MHz PCI operation was correctly
addressed (MSB/LSB problem). Now the correct currently setup
PCI frequency is displayed upon bootup.
This patch also fixes this problem on Rainier & Yellowstone, since these
boards use the same souce code as Sequoia & Yosemite do.
Signed-off-by: Stefan Roese <sr@denx.de>
At 133 MHz the current SDRAM refresh rate is too fast
(measured 4 * 1.17 us).
CFG_MAMR_PTA changes from 39 to 97. This result
in a refresh rate of 4 * 7.8 us at the default clock
50 MHz. At 133 MHz the value will be then 4 * 2.9 us.
This is a compromise until a new method is found to
adjust the refresh rate.
Signed-off-by: Martin Krause <martin.krause@tqs.de>
