Commit graph

684 commits

Author SHA1 Message Date
Christophe Leroy
ee1e600c13 powerpc: mpc8xx: Change CONFIG_8xx to CONFIG_MPC8xx
CONFIG_8xx doesn't mean much outside of arch/powerpc/
This patch renames it CONFIG_MPC8xx just like CONFIG_MPC85xx etc ...
It also renames 8xx_immap.h to immap_8xx.h to be consistent with
other file names.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2018-04-06 16:30:37 -04:00
Jagan Teki
89d4fc153b spi: atmel: default y if DM_SPI && ARCH_AT91
ATMEL_SPI is now fully converted to driver-model and
respective boards switch to DM_SPI as well,
so make default y for ARCH_AT91

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06 16:11:09 -04:00
Jagan Teki
37434db29b spi: atmel: Drop atmel_spi.h
atmel_spi.h has register offsets, and atmel_spi_slave
structure, move it into .c file for better readability
and drop atmel_spi.h

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06 16:11:09 -04:00
Jagan Teki
7b09477873 spi: atmel: Drop non-dm code
All board configs are now enabled DM_SPI for SPL and
U-Boot proper, so now its time to drop non-dm code.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06 16:11:09 -04:00
Jagan Teki
9bf48e2ee8 spi: atmel: Add ifdef for DM_GPIO code
Few boards are configuring gpio directly from board instead
using drivers/gpio so add ifdef for DM_GPIO to compatible
for both the cases.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Wenyou Yang <wenyouya@gmail.com>
2018-04-06 16:11:09 -04:00
Sjoerd Simons
63018a3edd omap3: spi: Correct ti, pindir-d0-out-d1-in parsing
The ti,pindir-d0-out-d1-in property is not expected to have a value
according to the device-tree binding, so treat it as a boolean not a
uint property.

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-23 23:03:29 +05:30
Eugeniy Paltsev
4b5f6c52e7 DW SPI: use 32 bit access instead of 16 and 32 bit mix
Current DW SPI driver uses 32 bit access for some registers and
16 bit access for others. So if DW SPI IP is connected via bus
which doesn't support 16 bit access we will get bus error.

Fix that by switching to 32 bit access only instead of 16 and 32 bit mix

Additional Documentation to Support this Change:
The DW_apb_ssi databook states:
"All registers in the DW_apb_ssi are addressed at 32-bit boundaries
to remain consistent with the AHB bus. Where the physical size of
any register is less than 32-bits wide, the upper unused bits of
the 32-bit boundary are reserved. Writing to these bits has no
effect; reading from these bits returns 0." [1]

[1] Section 6.1 of dw_apb_ssi.pdf (version 3.22a)

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22 23:01:35 +05:30
Eugeniy Paltsev
bcdcb3e61e DW SPI: add option to use external gpio for chip select
DW SPI internal chip select management has limitation:
it hold CS line in active state only when the FIFO is not
empty. If the FIFO freed before we add new data the SPI transaction will
be broken.

So add option to use external gpio for chip select. Gpio can be added
via device tree using standard gpio bindings.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22 23:01:35 +05:30
Eugeniy Paltsev
d3d8aaec74 DW SPI: refactor poll_transfer functions
There is no sense in waiting for RX data in dw_reader function:
there is no chance that RX data will appear in RX FIFO if
RX FIFO is empty after previous TX write in dw_writer function.
So get rid of this waiting. After that we can get rid of dw_reader
return value and make it returning void. After that we can get rid
of dw_reader return value check in poll_transfer function.

With these changes we're getting closer to Linux DW SPI driver.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22 23:01:35 +05:30
Eugeniy Paltsev
fc282c7bcb DW SPI: fix transmit only mode
In current implementation we get -ETIMEDOUT error when we try to use
transmit only mode (SPI_TMOD_TO)
This happens because in transmit only mode input FIFO never gets any data
which breaks our logic in dw_reader(): we are waiting until RX data will be
ready in dw_reader, but this newer happens, so we return with error.

Fix that by using SPI_TMOD_TR instead of SPI_TMOD_TO which allows to use
RX FIFO.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22 23:01:35 +05:30
Eugeniy Paltsev
c6b4f031d9 DW SPI: fix tx data loss on FIFO flush
In current implementation if some data still exists in Tx FIFO it
can be silently flushed, i.e. dropped on disabling of the controller,
which happens when writing 0 to DW_SPI_SSIENR (it happens in the
beginning of new transfer)

So add wait for current transmit operation to complete to be sure
that current transmit operation is finished before new one.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-03-22 23:01:35 +05:30
Tom Rini
3fa9bc7969 Merge git://git.denx.de/u-boot-spi 2018-03-15 08:27:27 -04:00
Jagan Teki
b2b41d2777 spi: omap3: Fix redeclared error
omap3_spi_set_speed|mode redeclared bus symbol, fix the same.

error:
drivers/spi/omap3_spi.c: In function ‘omap3_spi_set_speed’:
drivers/spi/omap3_spi.c:650:18: error: ‘bus’ redeclared as different kind of symbol
  struct udevice *bus = dev->parent;

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-14 23:19:31 +05:30
Patrice Chotard
aa5e3e22f4 board: stm32: switch to DM STM32 timer
Use available DM stm32_timer driver instead of dedicated
mach-stm32/stm32fx/timer.c.

Remove all defines or files previously used for timer usage in
arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx

Enable DM STM32_TIMER for STM32F4/F7 and H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
2018-03-13 21:45:37 -04:00
Jagan Teki
8480792287 spi: omap3: Skip set_mode, set_speed from claim
set_mode, set_seed functions has separate function pointers
in dm_spi_ops, so use them in relevent one instead of
calling from claim_bus.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13 19:50:10 +05:30
Jagan Teki
15927aef02 spi: atcspi200: Drop non-dm code
Boards adp-ae3xx_defconfig, nx25-ae250_defconfig
already enabled DM_SPI, so non-dm code make no use
of it hence droped.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2018-03-13 19:50:10 +05:30
Tuomas Tynkkynen
fbca0e66cc spi: Migrate CONFIG_CF_SPI to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:01:44 -05:00
Tuomas Tynkkynen
4a942f49b8 spi: Migrate CONFIG_KIRKWOOD_SPI to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:01:44 -05:00
Tuomas Tynkkynen
2c4b096b4c spi: Migrate CONFIG_LPC32XX_SSP to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:01:44 -05:00
Tuomas Tynkkynen
bbdf38698e spi: Migrate CONFIG_MPC8XXX_SPI to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:01:44 -05:00
Tuomas Tynkkynen
60e5456291 spi: Migrate CONFIG_MXC_SPI to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:01:44 -05:00
Tuomas Tynkkynen
7b819b569e spi: Migrate CONFIG_MXS_SPI to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:00:53 -05:00
Tuomas Tynkkynen
a5dfabea19 spi: Migrate CONFIG_SH_QSPI to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:00:47 -05:00
Tuomas Tynkkynen
95d3877a58 spi: Migrate CONFIG_SH_SPI to Kconfig
Signed-off-by: Tuomas Tynkkynen <tuomas@tuxera.com>
2018-02-13 23:00:29 -05:00
Heinrich Schuchardt
923837e159 atcspi200: avoid possible NULL dereference
Check if ns before and not after dereferencing it.

Indicated by cppcheck.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2018-02-07 22:06:18 -05:00
Tom Rini
1d12a7c8cd Merge git://git.denx.de/u-boot-spi 2018-01-26 07:46:34 -05:00
Eugeniy Paltsev
58c125b9e2 DW SPI: Get clock value from Device Tree
Add option to set spi controller clock frequency via device tree
using standard clock bindings.

Define dw_spi_get_clk function as 'weak' as some targets
(like SOCFPGA_GEN5 and SOCFPGA_ARRIA10) don't use standard clock API
and implement dw_spi_get_clk their own way in their clock manager.

Get rid of clock_manager.h include as we don't use
cm_get_spi_controller_clk_hz function anymore. (we use redefined
dw_spi_get_clk in SOCFPGA clock managers instead)

Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-26 11:26:16 +05:30
Vignesh R
aaa21d3ffc spi: cadence_qspi_apb: Make flash writes 32 bit aligned
Make flash writes 32 bit aligned by using bounce buffers to deal with
non 32 bit aligned buffers.
This is required because as per TI K2G TRM[1], the external master is
only permitted to issue 32-bit data interface writes until the last word
of an indirect transfer. Otherwise indirect writes is known to fail
sometimes.

[1] http://www.ti.com/lit/ug/spruhy8g/spruhy8g.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Vignesh R
a743e2ba38 Revert "spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible"
This reverts commit 57897c13de.

Using bounce_buf.c to handle non-DMA alignment problems is bad as
bounce_buf.c does cache manipulations which is not required. Therefore
revert this patch in favour of local bounce buffer solution in the next
patch.

Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Goldschmidt Simon
948ad4f075 Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible"
This reverts commit b63b46313e.

This commit changed cadence_qspi_apb to use bouncebuf.c, which invalidates
the data cache after reading. This is meant for dma transfers only and
breaks the cadence_qspi driver which copies via cpu only: data that is
copied by the cpu is in cache only and the cache invalidation at the end
throws away this data.

Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:11:36 +05:30
Jason Rush
15a70a5da3 spi: cadence_spi: Sync DT bindings with Linux
Adopt the Linux DT bindings. This also fixes an issue
with the indaddrtrig register on the Cadence QSPI
device being programmed with the wrong value for the
socfpga arch.

Tested on TI K2G platform:
Tested-by: Vignesh R <vigneshr@ti.com>

Tested on a socfpga-cyclonev board:
Tested-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>

Signed-off-by: Jason Rush <jarush@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
Acked-by: Marek Vasut <marex@denx.de>
2018-01-24 12:07:50 +05:30
Chris Packham
df16881cea spi: kirkwood_spi: implement workaround for FE-9144572
Erratum NO. FE-9144572: The device SPI interface supports frequencies of
up to 50 MHz.  However, due to this erratum, when the device core clock
is 250 MHz and the SPI interfaces is configured for 50MHz SPI clock and
CPOL=CPHA=1 there might occur data corruption on reads from the SPI
device.

Implement the workaround by setting the TMISO_SAMPLE value to 0x2
in the timing1 register.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:04:08 +05:30
Mario Six
24fc1ec2ee spi: spi-uclass: Fix style violations
Remove a superfluous newline, and reduce the scope of a variable.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:08 +05:30
Mario Six
184fa1c8da spi: Remove spi_setup_slave_fdt
A previous patch removed the spi_flash_probe_fdt function, which
contained the last call of the spi_setup_slave_fdt function, which is
now equally obsolete.

This patch removes the function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:07 +05:30
Mario Six
c5b88f29ba spi: Remove obsolete spi_base_setup_slave_fdt
0efc024 ("spi_flash: Add spi_flash_probe_fdt() to locate SPI by FDT
node") added a helper function spi_base_setup_slave_fdt to to set up a
SPI slave from a given FDT blob. The only user was the exynos SPI
driver.

But commit 73186c9 ("dm: exynos: Convert SPI to driver model") removed
the use of this function, hence rendering it obsolete.

Remove this function, as well as the CONFIG_OF_SPI option, which guarded
only this function.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Mario Six <mario.six@gdsys.cc>
2018-01-24 12:04:07 +05:30
Mario Six
547bcc3d18 spi: Fix style violation and improve code
This patch fixes a printf specifier style violation, reduces the scope
of a variable, and turns a void pointer that is used with pointer
arithmetic into a u8 pointer.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:04:07 +05:30
Álvaro Fernández Rojas
29cc4368ad dm: spi: add BCM63xx HSSPI driver
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx-hsspi.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:04:06 +05:30
Álvaro Fernández Rojas
5ac07d2969 dm: spi: add BCM63xx SPI driver
This driver is a simplified version of linux/drivers/spi/spi-bcm63xx.c

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Álvaro Fernández Rojas
48263504c8 wait_bit: use wait_for_bit_le32 and remove wait_for_bit
wait_for_bit callers use the 32 bit LE version

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2018-01-24 12:03:43 +05:30
Adam Ford
26410c1517 Convert CONFIG_DAVINCI_SPI to Kconfig
This converts the following to Kconfig:
   CONFIG_DAVINCI_SPI

Signed-off-by: Adam Ford <aford173@gmail.com>
2018-01-22 16:43:30 -05:00
Peng Fan
afe8e1b033 spi: fsl_qspi: support i.MX6UL/6ULLL/7D
The QSPI module on i.MX7D is modified from i.MX6SX. The module used on
i.MX6UL/6ULL is reused from i.MX7D. They share same tx buffer size.

The endianness is not set at qspi driver initialization. So if we don't
boot from QSPI, we will get wrong endianness when accessing from AHB
address directly.

Add the compatible entry for 6ul/7d.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-01-12 14:28:04 +01:00
Rick Chen
6720e4ae7a cosmetic: atcspi200: Rename function name as atcspi200
Integrate function and struct name from ae3xx to
atcspi200 will be more reasonable.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 09:45:21 +08:00
Rick Chen
41bbb8b333 spi: nds_ae3xx: Rename nds_ae3xx_spi as atcspi200_spi
atcspi200 is Andestech spi ip which is embedded in
AE3XX and AE250 platforms. So rename as atcspi200
will be more reasonable to be used in different
platforms.

Signed-off-by: Rick Chen <rick@andestech.com>
2017-11-30 09:44:09 +08:00
Heinrich Schuchardt
11f12c17d7 rockchip: spi: the symbol for Hertz is Hz
fix typo

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-11-21 23:57:23 +01:00
Heinrich Schuchardt
042de609ed omap3: spi: the symbol for Hertz is Hz
fix typo

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2017-11-20 20:18:40 -05:00
Bin Meng
ab20107468 spi: ich: Lock down controller settings if required
Some Intel FSP (like Braswell) does SPI lock-down during the call
to fsp_notify(INIT_PHASE_BOOT). But before SPI lock-down is done,
it's bootloader's responsibility to configure the SPI controller's
opcode registers properly otherwise SPI controller driver doesn't
know how to communicate with the SPI flash device.

Rather than passively doing the opcode configuration, let's add a
simple DTS property "intel,spi-lock-down" and let the driver call
the opcode configuration function if required by such FSP.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-10-27 15:13:47 +08:00
Tuomas Tynkkynen
95688de311 spi: Drop CONFIG_ATMEL_DATAFLASH_SPI
Last user of this option went away in commit:

fdc7718999 ("board: usb_a9263: Update to support DT and DM")

Signed-off-by: Tuomas Tynkkynen <tuomas.tynkkynen@iki.fi>
Acked-by: Wenyou Yang <wenyou.yang@microchip.com>
2017-10-16 09:42:51 -04:00
Masahiro Yamada
9b643e312d treewide: replace with error() with pr_err()
U-Boot widely uses error() as a bit noisier variant of printf().

This macro causes name conflict with the following line in
include/linux/compiler-gcc.h:

  # define __compiletime_error(message) __attribute__((error(message)))

This prevents us from using __compiletime_error(), and makes it
difficult to fully sync BUILD_BUG macros with Linux.  (Notice
Linux's BUILD_BUG_ON_MSG is implemented by using compiletime_assert().)

Let's convert error() into now treewide-available pr_err().

Done with the help of Coccinelle, excluing tools/ directory.

The semantic patch I used is as follows:

// <smpl>
@@@@
-error
+pr_err
 (...)
// </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Re-run Coccinelle]
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-10-04 11:59:44 -04:00
Adam Ford
ab0ac27242 spi: davinci_spi: Add da830-spi support for DM
The DM support is already in the driver, so add
da830-spi to the compatible list.

Reviewed-by: Jagan Teki <jagan@openedev.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
2017-09-29 10:52:20 -04:00
Suresh Gupta
1050998728 spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kumar_1@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25 15:45:15 +05:30
Suresh Gupta
1c631da459 spi: fsl_qspi: Add controller busy check before new spi operation
It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-09-25 12:49:56 +05:30
Peng Fan
994266bdff spi: mxc_spi: support driver model
Add driver model support for mxc spi driver.
Most functions are restructured to be reused by DM and non-DM.
Tested on mx6slevk/mx6qsabresd board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2017-09-25 12:47:59 +05:30
rick
7155cd2e6e nds32: spi: Support spi dm driver.
Support spi driver and can detect MX25U1635E flash on AE3XX board.

Verification:

sf probe 0:0 50000000 0
spi_flash_std_probe(sf_Probr.c)
	spi_flash_probe_slave(sf_Probr.c)
	SF: Detected mx25u1635e with page size 256 Bytes, erase size 4 KiB, total 2 MiB
	NDS32 # sf test 0x100000 0x1000
	SPI flash test:
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps
	Test passed
	0 erase: 34 ticks, 117 KiB/s 0.936 Mbps
	1 check: 15 ticks, 266 KiB/s 2.128 Mbps
	2 write: 21 ticks, 190 KiB/s 1.520 Mbps
	3 read: 11 ticks, 363 KiB/s 2.904 Mbps

Signed-off-by: rick <rick@andestech.com>
2017-09-21 10:30:22 +08:00
Philipp Tomsich
d27c273908 rockchip: spi: Convert to livetree
Update the Rockchip SPI driver to support a live device tree.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-09-18 20:40:35 +02:00
Bin Meng
d2ca80c3d7 x86: ich-spi: Clear atomic preop only when SPI settings are not locked
The atomic preop register can only be written when SPI settings are
not locked, otherwise it's read-only.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
52dd56ba84 x86: ich-spi: Remove useless assignment in ich_spi_xfer()
In ich_spi_xfer() when the driver presets control fields, control
variable gets assigned twice. Apparently only the last assignment
takes effect. Remove the other one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-09-02 23:35:55 +08:00
Bin Meng
b42711f90c x86: ich-spi: Move opcode registers configuration to another routine
At present the ICH SPI opcode registers configuration is done in the
ich_spi_remove() routine, a little bit weird but that's how current.
Linux MTD driver works. This changes to move the opcode registers
configuration to a separate routine ich_spi_config_opcode() which
might be called by U-Boot itself as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
3e79141684 x86: ich-spi: Don't read cached lock status
At present the ICH SPI controller driver reads the controller lock
status from its register in the probe routine and saves the lock
status to a member of priv. Later the driver uses the cached status
from priv to judge whether the controller setting is locked and do
different setup.

But such logic is only valid when there is only the SPI controller
driver that touches the SPI hardware. In fact the lock status change
can be trigged outside the driver, eg: during the fsp_notify() call
when Intel FSP is used.

This changes the driver to read the lock status every time when an
SPI transfer is initiated instead of reading the cached one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
7d82978927 x86: ich-spi: Remove unnecessary assignment in ich_init_controller()
There is no need to do another assignment to ich7_spi.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Bin Meng
94bc9177ca x86: ich-spi: Remove spi_write_protect_region()
This routine is not called anywhere.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2017-08-24 11:00:47 +08:00
Tom Rini
c1b62ba9ca Merge branch 'master' of git://git.denx.de/u-boot-rockchip 2017-08-14 10:40:01 -04:00
Philipp Tomsich
d16120a6de rockchip: spi: enable support for the rk_spi driver for the RK3368
For the RK3368, we can reuse the SPI driver (although we'll have to
eventually investigate whether it can be merged with the
designware_spi.c driver) also used for the RK3288 and RK3399.
This adds the necessary compatible string to support the RK3368.

Note that the assumption that GPLL will be clocked at 594MHz is not
true for the RK3368, but this will not lead to incorrect functioning
(just to a lower-than-expected SPI operating frequency): this has been
documented in the driver, so it doesn't cause any headaches when
someone next needs to touch the clock code of this driver.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-08-13 17:12:34 +02:00
Adam Ford
a41e3e1480 OMAP3_SPI: Kconfig: move OMAP3_SPI out of DM_SPI section.
The OMAP3_SPI driver can work with or without DM_SPI.  Moving this
outside of the #if DM_SPI section allows us to include it on boards
that don't support DM_SPI yet.

Signed-off-by: Adam Ford <aford173@gmail.com>
2017-08-12 19:17:20 -04:00
Tom Rini
ec7483e34e Merge git://git.denx.de/u-boot-fsl-qoriq
Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
	include/configs/ls1046aqds.h
	include/configs/ls1046ardb.h
2017-08-02 10:52:26 -04:00
Alexander Stein
4df24f2c40 spi: fsl_qspi: Pet watchdog even more
Pet the watchdog once upon each command call (qspi_xfer) and during
each loop iteration in several commands.

This fixes a watchdog reset especially during erase command.

Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-08-01 08:28:56 -07:00
Simon Glass
28a3e5a864 dm: tegra: spi: Convert to livetree
Update the tegra114 spi driver to support a live device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Simon Glass
000f15fa15 dm: tegra: Convert clock_decode_periph_id() to support livetree
Adjust this to take a device as a parameter instead of a node.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-on: Beaver, Jetson-TK1
Tested-by: Stephen Warren <swarren@nvidia.com>
2017-07-28 12:02:47 -06:00
Patrice Chotard
541cd6e54e spi: stm32_qspi: add clk_get_rate() support
Replace proprietary clock_get() by clk_get_rate()
The stm32_qspi is now "generic" and can be used
by other STM32 SoCs.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
2017-07-26 11:28:08 -04:00
Stefano Babic
552a848e4f imx: reorganize IMX code as other SOCs
Change is consistent with other SOCs and it is in preparation
for adding SOMs. SOC's related files are moved from cpu/ to
mach-imx/<SOC>.

This change is also coherent with the structure in kernel.

Signed-off-by: Stefano Babic <sbabic@denx.de>

CC: Fabio Estevam <fabio.estevam@nxp.com>
CC: Akshay Bhat <akshaybhat@timesys.com>
CC: Ken Lin <Ken.Lin@advantech.com.tw>
CC: Marek Vasut <marek.vasut@gmail.com>
CC: Heiko Schocher <hs@denx.de>
CC: "Sébastien Szymanski" <sebastien.szymanski@armadeus.com>
CC: Christian Gmeiner <christian.gmeiner@gmail.com>
CC: Stefan Roese <sr@denx.de>
CC: Patrick Bruenn <p.bruenn@beckhoff.com>
CC: Troy Kisky <troy.kisky@boundarydevices.com>
CC: Nikita Kiryanov <nikita@compulab.co.il>
CC: Otavio Salvador <otavio@ossystems.com.br>
CC: "Eric Bénard" <eric@eukrea.com>
CC: Jagan Teki <jagan@amarulasolutions.com>
CC: Ye Li <ye.li@nxp.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Adrian Alonso <adrian.alonso@nxp.com>
CC: Alison Wang <b18965@freescale.com>
CC: Tim Harvey <tharvey@gateworks.com>
CC: Martin Donnelly <martin.donnelly@ge.com>
CC: Marcin Niestroj <m.niestroj@grinn-global.com>
CC: Lukasz Majewski <lukma@denx.de>
CC: Adam Ford <aford173@gmail.com>
CC: "Albert ARIBAUD (3ADEV)" <albert.aribaud@3adev.fr>
CC: Boris Brezillon <boris.brezillon@free-electrons.com>
CC: Soeren Moch <smoch@web.de>
CC: Richard Hu <richard.hu@technexion.com>
CC: Wig Cheng <wig.cheng@technexion.com>
CC: Vanessa Maegima <vanessa.maegima@nxp.com>
CC: Max Krummenacher <max.krummenacher@toradex.com>
CC: Stefan Agner <stefan.agner@toradex.com>
CC: Markus Niebel <Markus.Niebel@tq-group.com>
CC: Breno Lima <breno.lima@nxp.com>
CC: Francesco Montefoschi <francesco.montefoschi@udoo.org>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Scott Wood <oss@buserror.net>
CC: Joe Hershberger <joe.hershberger@ni.com>
CC: Anatolij Gustschin <agust@denx.de>
CC: Simon Glass <sjg@chromium.org>
CC: "Andrew F. Davis" <afd@ti.com>
CC: "Łukasz Majewski" <l.majewski@samsung.com>
CC: Patrice Chotard <patrice.chotard@st.com>
CC: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
CC: Hans de Goede <hdegoede@redhat.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stephen Warren <swarren@nvidia.com>
CC: Andre Przywara <andre.przywara@arm.com>
CC: "Álvaro Fernández Rojas" <noltari@gmail.com>
CC: York Sun <york.sun@nxp.com>
CC: Xiaoliang Yang <xiaoliang.yang@nxp.com>
CC: Chen-Yu Tsai <wens@csie.org>
CC: George McCollister <george.mccollister@gmail.com>
CC: Sven Ebenfeld <sven.ebenfeld@gmail.com>
CC: Filip Brozovic <fbrozovic@gmail.com>
CC: Petr Kulhavy <brain@jikos.cz>
CC: Eric Nelson <eric@nelint.com>
CC: Bai Ping <ping.bai@nxp.com>
CC: Anson Huang <Anson.Huang@nxp.com>
CC: Sanchayan Maity <maitysanchayan@gmail.com>
CC: Lokesh Vutla <lokeshvutla@ti.com>
CC: Patrick Delaunay <patrick.delaunay@st.com>
CC: Gary Bisson <gary.bisson@boundarydevices.com>
CC: Alexander Graf <agraf@suse.de>
CC: u-boot@lists.denx.de
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-07-12 10:17:44 +02:00
Philipp Tomsich
6c65577ce6 rockchip: spi: dm: convert fdt_get to dev_read
With the new dev_read functions available, we can convert the rockchip
architecture-specific drivers and common drivers used by these devices
over to the dev_read family of calls.

This change covers the rk_spi.c (SPI driver) used in Rockchip devices.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2017-07-11 12:13:43 +02:00
Christophe Leroy
f88c431b8a powerpc, 8xx: move SPI driver to drivers/spi/
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
2017-07-08 15:56:03 -04:00
Andy Shevchenko
daab59ac05 avr32: Retire AVR32 for good
AVR32 is gone. It's already more than two years for no support in Buildroot,
even longer there is no support in GCC (last version is heavily patched 4.2.4).

Linux kernel v4.12 got rid of it (and v4.11 didn't build successfully).

There is no good point to keep this support in U-Boot either.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2017-07-06 16:17:19 -04:00
Simon Glass
4a7b9ee15e tegra: spi: Wait a little after setting the clocks
For devices that need a delay between SPI transactions we seem to need an
additional delay before the first one if the CPU is running at full speed.
Add this, under control of the existing setting. At present it will only
be enabled with the Chrome OS EC.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-09 13:39:33 -06:00
Simon Glass
279e26f5a3 dm: spi: Convert uclass to livetree
Update the SPI uclass to support a live device tree. Also adjust
spi_slave_ofdata_to_platdata() to accept a device instead of a blob and
offset.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:16 -06:00
Simon Glass
150c5afe5b dm: gpio: Add live tree support
Add support for requesting GPIOs with a live device tree.

This involves adjusting the function signature for the legacy function
gpio_request_by_name_nodev(), so fix up all callers.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes to stm32f746-disco.c:
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-06-01 07:03:10 -06:00
Simon Glass
da409ccc4a dm: core: Replace of_offset with accessor (part 2)
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:04 -06:00
Simon Glass
4af0d7e870 dm: Fix up inclusion of common.h
It is good practice to include common.h as the first header. This ensures
that required features like the DECLARE_GLOBAL_DATA_PTR macro,
configuration options and common types are available.

Fix up some files which currently don't do this. This is necessary because
driver model will soon start using global data and configuration in the
dm/read.h header file, included via dm.h. The gd->fdt_blob value will be
used to access the device tree and CONFIG options will be used to
determine whether to support inline functions in the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:03 -06:00
Simon Glass
a821c4af79 dm: Rename dev_addr..() functions
These support the flat device tree. We want to use the dev_read_..()
prefix for functions that support both flat tree and live tree. So rename
the existing functions to avoid confusion.

In the end we will have:

   1. dev_read_addr...()    - works on devices, supports flat/live tree
   2. devfdt_get_addr...()  - current functions, flat tree only
   3. of_get_address() etc. - new functions, live tree only

All drivers will be written to use 1. That function will in turn call
either 2 or 3 depending on whether the flat or live tree is in use.

Note this involves changing some dead code - the imx_lpi2c.c file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-06-01 07:03:01 -06:00
Peng Fan
41eb8ff5ea spi: kconfig: add soft spi Kconfig entry
Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the
SPI signals. We use it for accessing 74x164 on some i.MX boards.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
2017-05-18 11:24:34 +02:00
Stefan Roese
4759dffe23 spi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exit
This patch adds a remove function to the Intel ICH SPI driver, that will
be called upon U-Boot exit, directly before the OS (Linux) is started.
This function takes care of configuring the BIOS registers in the SPI
controller (similar to what a "standard" BIOS or coreboot does), so that
the Linux MTD device driver is able to correctly read/write to the SPI
NOR chip. Without this, the chip is not detected at all.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Jagan Teki <jteki@openedev.com>
2017-05-17 17:13:06 +08:00
Tom Rini
25eaa28801 omap: spi: Drop CONFIG_OMAP3_SPI_D0_D1_SWAPPED support
This particular quirk is not enabled in any config files today.  It does
however exist and is handled correctly in device trees and via
CONFIG_DM_SPI.  So we drop the symbol now and add a comment to indicate
that any (new) boards that require this quirk need to enable DM_SPI
instead.

Signed-off-by: Tom Rini <trini@konsulko.com>
2017-05-15 10:40:01 -04:00
Jakob Unterwurzacher
cdeb4d780a rockchip: spi: enable support for the rk_spi driver for the RK3399
The existing Rockchip SPI (rk_spi.c) driver also matches the hardware
block found in the RK3399.  This has been confirmed both with SPI NOR
flashes and general SPI transfers on the RK3399-Q7 for SPI1 and SPI5.

This change adds the 'rockchip,rk3399-spi' string to its compatible
list to allow reuse of the existing driver.

X-AffectedPlatforms: RK3399-Q7
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Jakob Unterwurzacher <jakob.unterwurzacher@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
9fc354e246 rockchip: spi: rewrite rkspi_set_clk for a more conservative baudrate setting
The baudrate in rkspi was calculated by using an integer division
(which implicitly discarded any fractional result), then rounding to
an even number and finally clamping to 0xfffe using a bitwise AND
operator.  This introduced two issues:
1) for very small baudrates (overflowing the 0xfffe range), the
   bitwise-AND generates rather random-looking (wildly varying)
   actual output bitrates
2) for higher baudrates, the calculation tends to 'err towards a
   higher baudrate' with the actual error increasing as the dividers
   become very small. E.g., with a 99MHz input clock, a request
   for a 20MBit baudrate (99/20 = 4.95), a 24.75 MBit would be use
   (which amounts to a 23.75% error)... for a 34 MBit request this
   would be an actual outbout of 49.5 Mbit (i.e. a 45% error).

This change rewrites the divider selection (i.e. baudrate calculation)
by making sure that
a) for the normal case: the largest representable baudrate below the
   requested rate will be chosen;
b) for the denormal case (i.e. when the divider can no longer be
   represented), the lowest representable baudrate is chosen.

Even though the denormal case (b) may be of little concern in real
world applications (even with a 198MHz input clock, this will only
happen at below approx. 3kHz/3kBit), our board-verification team kept
complaining.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
2017-05-10 13:37:21 -06:00
Philipp Tomsich
bd37671434 rockchip: spi: rk_spi: dynamically select an module input rate
The original clock/bitrate selection code for the rk_spi driver was a
bit limited, as it always selected a 99MHz input clock rate (which
would allow for a maximum bitrate of 49.5MBit/s), but returned -EINVAL
if a bitrate higher than 48MHz was requested.

To give us better control over the bitrate (i.e. add more operating
points, especially at "higher" bitrate---such as above 9MBit/s), we
try to choose 4x the maximum frequency (clamped to 50MBit) from the
DTS instead of 99MHz... for most use-cases this will yield a frequency
of 198MHz, but is flexible to go beyond this in future configurations.

This also rewrites the check to allow frequencies of up to half the
SPI module rate as bitrates and then clamps to whatever the DTS allows
as a maximum (board-specific) frequency and does away with the -EINVAL
when trying to select a bitrate (for cases that exceeded the hard
limit) and instead consistently clamps to the lower of the hard limit,
the soft limit for the SPI bus (from the DTS) or the soft limit for
the SPI slave device.

This replaces
  "rockchip: spi: rk_spi: select 198MHz input to the SPI module for the RK3399"
  "rockchip: spi: rk_spi: improve clocking code for the RK3399"
from earlier versions of this series.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2017-05-10 13:37:21 -06:00
Vikas Manocha
890bafd752 stm32f7: use clock driver to enable qspi controller clock
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
2017-05-08 11:38:41 -04:00
Suniel Mahesh
2f54205829 drivers: spi: Remove duplicate .probe method
.probe method has been assigned twice when declaring
a driver with U_BOOT_DRIVER(). Removed one of them.
Here is the last commit which had the duplicate entry:
"spi: omap3: Convert to driver model"
(sha1: 77b8d04854)

Signed-off-by: Suniel Mahesh <suniel.spartan@gmail.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03 11:52:16 +05:30
Moritz Fischer
ac6991fb5f zynq: spi: Honour the activation / deactivation delay
This is not currently implemented. Add support for this so that the
Chrome OS EC can be used reliably.

Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Acked-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03 11:03:04 +05:30
Wenyou Yang
61a77ce1d5 spi: atmel: check GPIO validity before using cs_gpios
Before using the cs_gpio, check if the GPIO is valid or not.

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-05-03 10:58:54 +05:30
Tom Rini
ea3310e8aa Blackfin: Remove
The architecture is currently unmaintained, remove.

Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
2017-04-05 13:52:01 -04:00
Stefan Roese
706865afe5 dm: core: Add flags parameter to device_remove()
This patch adds the flags parameter to device_remove() and changes all
calls to this function to provide the default value of DM_REMOVE_NORMAL
for "normal" device removal.

This is in preparation for the driver specific pre-OS (e.g. DMA
cancelling) remove support.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>
2017-04-04 20:15:10 -06:00
Suresh Gupta
38a5c57ac5 spi: fsl_qspi: Add support for single chip select
SOC’s like LS1012A has only one chip select signal for QSPI flash.
Avoid scanning other flash.

Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
2017-03-28 09:10:12 -07:00
Jean-Jacques Hiblot
b06a381a69 drivers: ti_qspi: use syscon to get the address ctrl_mod_mmap register
We used to get the address of the optionnal ctrl_mod_mmap register as the
third memory range of the "reg" property. the linux driver moved to use a
syscon instead. In order to keep the DTS as close as possible to that of
linux, we move to using a syscon as well.

If SYSCON is not supported, the driver reverts to the old way of getting
the address from the 3rd memory range

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2017-03-22 07:27:19 -06:00
Simon Glass
e160f7d430 dm: core: Replace of_offset with accessor
At present devices use a simple integer offset to record the device tree
node associated with the device. In preparation for supporting a live
device tree, which uses a node pointer instead, refactor existing code to
access this field through an inline function.

Signed-off-by: Simon Glass <sjg@chromium.org>
2017-02-08 06:12:14 -07:00
Michael Kurz
d4363baada ARM: SPI: stm32: add stm32f746 qspi driver
This patch adds support for the QSPI IP found in stm32f7 devices.

Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
2017-01-28 14:04:50 -05:00
Jagan Teki
68e7999ba9 spi: Zap cf_qspi driver and related code
Dropped becuase
- driver not used any board.
- no dm conversion.

Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Richard Retanubun <richardretanubun@ruggedcom.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Acked-by: Angelo Dureghello <angelo@sysam.it>
2017-01-15 18:29:04 +01:00
Jagan Teki
ee86e0d2fe spi: Zap ep93xx_spi driver and related code
Dropped becuase
- driver and related configs not used any board.
- no dm conversion.

Cc: Heiko Schocher <hs@denx.de>
Cc: Sergey Kostanbaev <sergey.kostanbaev@gmail.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
2017-01-13 22:47:14 +01:00
Vignesh R
b63b46313e spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:38:35 +01:00
Vignesh R
57897c13de spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.

So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.

[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf

Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Jagan Teki <jagan@openedev.com>
2017-01-04 16:38:12 +01:00
Jagan Teki
cb71c6d854 spi: Zap armada100_spi.c and env
armada100_spi.c and related env is zapping becuase
of "no DM conversion".

Cc: Ajay Bhargav <ajay.bhargav@einfochips.com>
Signed-off-by: Jagan Teki <jagan@openedev.com>
2016-12-21 12:18:47 +01:00
Jagan Teki
353f6a770f spi: Zap mpc52xx_spi.c, config and related code
armada100_spi.c, related config options and related codes
are zapping becuase of "no DM conversion".

Cc: Werner Pfister <Pfister_Werner@intercontrol.de>
Signed-off-by: Jagan Teki <jagan@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2016-12-21 12:14:37 +01:00